例2:设计一双向8位总线驱动器 LIBRARY IEEE: USE IEEE STD LOGIC 1164.ALL: ENTITY gd8 IS PORT( A, B: INOUT STD LOGIC VECTOR(7 DOWNTO0; EN, DIR: INSTD LOGIC); END gd8 aRChITECtURE behavior oF gd8 IS SIGNALAOUT, BOUT: STD LOGIC VECTOR(7 DOWNTO0); BEGIN AB: PROCESS(A,EN, DIR) IF((EN=OAND DIR=DTHEN BOUT<=A ELSE BOUT<=“mZD”; 为什么定 END IF 义信号? B<=BOUT END PROCESS AB:例2：设计一双向8位总线驱动器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY qd8 IS PORT( A,B: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); EN,DIR:IN STD_LOGIC); END qd8; ARCHITECTURE behavior OF qd8 IS SIGNAL AOUT,BOUT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN AB:PROCESS(A,EN,DIR) IF ((EN=‘0’) AND (DIR=‘1’) THEN BOUT<=A; ELSE BOUT<=“ZZZZZZZZ”; END IF; B<=BOUT; END PROCESS AB; 为什么定 义信号？