系统可编程技不 第13讲 VHDL语言语言组合逻辑 电路设计
在系统可编程技术 第13讲 VHDL语言语言组合逻辑 电路设计
、逻辑门电路设计 例1:用数据流描述方式设计一个4输入“与或非”逻辑门 LIBRARY IEEE USE IEEE STD LOGIC 1164ALL ENTITY vhf Is PORT(A, B, C, D: IN STD LOGIC; OUT STD LOGIC); ENd yhf4 请画出 arChiteCture data flow Of yhf4 Is 电路图 BEGIN Y<=NOT(AAND B)OR (CAND D)); ENd data flow;
一、逻辑门电路设计 例1：用数据流描述方式设计一个4输入“与或非”逻辑门 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY yhf4 IS PORT(A,B,C,D: IN STD_LOGIC; Y: OUT STD_LOGIC); END yhf4; ARCHITECTURE data_flow OF yhf4 IS BEGIN Y<=NOT((A AND B) OR (C AND D)); END data_flow; 请画出 电路图
例2:设计一双向8位总线驱动器 LIBRARY IEEE: USE IEEE STD LOGIC 1164.ALL: ENTITY gd8 IS PORT( A, B: INOUT STD LOGIC VECTOR(7 DOWNTO0; EN, DIR: INSTD LOGIC); END gd8 aRChITECtURE behavior oF gd8 IS SIGNALAOUT, BOUT: STD LOGIC VECTOR(7 DOWNTO0); BEGIN AB: PROCESS(A,EN, DIR) IF((EN=OAND DIR=DTHEN BOUT<=A ELSE BOUT<=“mZD”; 为什么定 END IF 义信号? B<=BOUT END PROCESS AB:
例2：设计一双向8位总线驱动器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY qd8 IS PORT( A,B: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); EN,DIR:IN STD_LOGIC); END qd8; ARCHITECTURE behavior OF qd8 IS SIGNAL AOUT,BOUT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN AB:PROCESS(A,EN,DIR) IF ((EN=‘0’) AND (DIR=‘1’) THEN BOUT<=A; ELSE BOUT<=“ZZZZZZZZ”; END IF; B<=BOUT; END PROCESS AB; 为什么定 义信号？
例2:设计一双向8位总线驱动器 BA: PROCESS(B,EN DIR) IF(EN=O)AND IR=O)THEN AOUT<=B ELSE AOUT<=“ZDD”; END IF END PROCESS BA; A<=AOUT MUIDTH IN=8 WIDTH OUT=8 Bulbus. BOUT A[7.] WIDTH IN=8 WIDTH OUT=8 buibus AOUT
BA:PROCESS(B,EN,DIR) IF ((EN=‘0’) AND (DIR=‘0’) THEN AOUT<=B; ELSE AOUT<=“ZZZZZZZZ”; END IF; END PROCESS BA; A<=AOUT END behavior; 例2：设计一双向8位总线驱动器
例1:设计8-3优先权编码器 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL: enTiTY bmg83 IS PORT D IN STD LOGIC VECOR(7 DOWNTO 0); 二编码器设计 OUT STD LOGIC VECTOR(2 DOWNTO 0)); ENd bmg83 aRChItECtURE behavior OF bmg83 Is BEGIN PROCESS) BEGIN IFD(7=0 THEN Y<=“000”; ELSIF D(6=0 THEN Y<=“001”; ELSIF D(5)=“0 THEN Y<=“010”; 该描述具 ELSIF D(4)=0 THEN Y<=“011”; 有优先级 ELSIF D(3)=“0 THEN Y<=“100 ELSIF D(2=0 THEN Y<=“101”; ELSIF D(1)=0 THEN Y<=“110”; ELSIF D(0)=0 THEN Y<=“11”; ELSY<=“XXX”; END PROCESS END behavior;
二 编 码 器 设 计 例1：设计8－3优先权编码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmq83 IS PORT( D: IN STD_LOGIC_VECOR(7 DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END bmq83; ARCHITECTURE behavior OF bmq83 IS BEGIN PROCESS(D) BEGIN IF D(7)=‘0’ THEN Y<=“000”; ELSIF D(6)=‘0’ THEN Y<=“001”; ELSIF D(5)=‘0’ THEN Y<=“010”; ELSIF D(4)=‘0’ THEN Y<=“011”; ELSIF D(3)=‘0’ THEN Y<=“100”; ELSIF D(2)=‘0’ THEN Y<=“101”; ELSIF D(1)=‘0’ THEN Y<=“110”; ELSIF D(0)=‘0’ THEN Y<=“111”; ELS Y<=“XXX”; END PROCESS; END behavior; 该描述具 有优先级
例1:设计3-8线译码器 LIBRARY IEEE: USE IEEESTD LOGIC 1164ALL: ENTITY ymg 83 IS 译码器设计 PORT(A, B, C: IN STD LOGIC; Y: OUTSTD LOGIC VECTOR(7 DOWNTOO)) END ymq83; 请注意 数据类型 的声明
三 译 码 器 设 计 例1：设计3－8线译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ymq83 IS PORT(A,B,C: IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ymq83; 请注意 数据类型 的声明
例1:设计3-8线译码器 aRChitECtURE behavior oF ymg 83 IS SIGNAL INDATA: STD LOGIC VECTOR(2 DOWNTOO); BEGIN INDATAYYYYYYYY<=“ XXXXXXXX”; END CASE END PROCESS: END behavior;
ARCHITECTURE behavior OF ymq83 IS SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN INDATA Y Y Y Y Y Y Y Y Y<=“XXXXXXXX”; END CASE; END PROCESS; END behavior; 该描述 不具有 优先级 例1：设计3－8线译码器 译 码 器 设 计
四、运算器设计 例1:设计4位二进制加法器 LIBRARY IEEE: USE IEEESTD LOGIC 1164.ALLS USE IEEE STD LOGIC ARITHALL USE IEEE STD LOGIC UNSIGNEDALL: ENTITY ifq Is PORT a, b: IN STD LOGIC VECOR(3 DOWNTOO sum: OUTSTD LOGIC VECTOR(4 DOWNTOO) END jfq4: aRChITECTURE behavior oF ifg Is BEGIN 数据类 PROCESS(a, b) BEGIN 型必须 sum<=(0a)+(0&b); 致才 END PROCESS 能赋值 eNd behavior
四、运算器设计 例1：设计4位二进制加法器 数据类 型必须 一致才 能赋值 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY jfq4 IS PORT( a,b: IN STD_LOGIC_VECOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END jfq4; ARCHITECTURE behavior OF jfq4 IS BEGIN PROCESS(a,b) BEGIN sum<=(‘0’&a)+(‘0’&b); END PROCESS; END behavior;
四、运算器设计 例2:设计8位整数加法器 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL: USE IEEESTD LOGIC ARITH.ALL; ENTITY ifg 8 IS PORTO opl, op2: IN UNSIGNED(3 DOWNTO0); result: OUT INTEGER); END ifg aRChitECtURE behavior oF ifg IS BEGIN 将数据 result<=CONV INTEGER(OPI+OP2); 类型转 END behavior; 换为 致
例2：设计8位整数加法器 将数据 类型转 换为一 致 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY jfq8 IS PORT( op1,op2: IN UNSIGNED(3 DOWNTO 0); result: OUT INTEGER); END jfq8; ARCHITECTURE behavior OF jfq8 IS BEGIN result<=CONV_INTEGER(OP1+OP2); END behavior; 四、运算器设计
五、奇偶校验电路设计 例1:设计9位奇偶校验电路,输入数据中“1”的个数为奇 数时输出为“0”,否则输出为“1”。 LIBRARY IEEE: USE IEEESTD LOGIC 1164ALL: ENTITY jou9 Is PORTO a: IN STD LOGIC VECTOR (8 DOWNTO O); OUT STD LOGIC); END ioug
五、奇偶校验电路设计 例1：设计9位奇偶校验电路，输入数据中“1”的个数为奇 数时输出为“0”，否则输出为“1”。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY jou9 IS PORT( a: IN STD_LOGIC_VECTOR(8 DOWNTO 0); y: OUT STD_LOGIC); END jou9;
