系统可编程技不 第14讲 VHDL语言语言时序逻辑 电路设计
在系统可编程技术 第14讲 VHDL语言语言时序逻辑 电路设计
时钟的描述方法 CP=1 CP=1 CP=0 CP=0 CPEVENT CP EVENT CPEVENT 上升沿:CPEⅤ ENTAND CP=1 下升沿:CPEⅤ ENT AND CP=0
时钟的描述方法 上升沿：CP’EVENT AND CP=‘1’ 下升沿：CP’EVENT AND CP=‘0’ CP=0 CP=0 CP=1 CP=1 CP’EVENT CP’EVENT CP’EVENT
上升沿D触发器描述 方法一:使用信号属性函数 LIBRARY IEEE: USE IEEE STD LOGIC 1164ALL: ENTITY D reg Is PORTO, CP: IN STD LOGIC; Q: OUTSTD LOGIC); END D reg ARCHITECTURE test OFD reg Is BEGIN PROCESS(CP) BEGIN IF(CPEVENT AND CP=D)THEN Q<=D; END PROCESS END test:
上升沿D触发器描述 方法一：使用信号属性函数 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(CP) BEGIN IF (CP’EVENT AND CP=‘1’) THEN Q<=D; END PROCESS; END test;
上升沿D触发器描述 方法二:使用WAIT语句 BRARY EEE USE IEEESTD LOGIC 1164ALL: ENTITY D reg Is PORTOD,CP: IN STD LOGIC; Q: OUT STD LOGIC); END D reg: ARCHITECTURE test OFD reg Is BEGIN PROCESS BEGIN WAIT UNTIL CP=1 Q<=D END PROCESS END test
方法二：使用WAIT 语句 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS BEGIN WAIT UNTIL CP=‘1’; Q<=D; END PROCESS; END test; 上升沿D触发器描述
方法三:使用上升沿检测函数 LIBRARY IEEE: 上升沿 USE IEEESTD LOGIC 1164.ALL; ENTITY D reg Is PORTOD, CP: IN STD LOGIC; Q: OUT STD LOGIC) END D reg D触发器描述 ARCHITECTURE test OF D reg Is BEGIN PROCESS(P) BEGIN IF(rising edge(cp))THEN Q<=D END IF. END PROCESS END test:
方法三：使用上升沿检测函数 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(cp) BEGIN IF (rising_edge(cp)) THEN Q<=D; END IF; END PROCESS; END test; 上升沿D触发器描述
方法四:使用进程的启动特性 LIBRARY EEE USE IEEESTD LOGIC 1164.ALL 上升沿D一 ENTITY D reg Is PORTOD, CP: IN STD LOGIC; Q: OUT STD LOGIC); END D reg; ARCHITECTURE test OFD reg Is BEGIN 触发器描述 PROCESS (CP) BEGIN IFCP=1’THEN Q<=D END IF: END PROCESS END test:
方法四：使用进程的启动特性 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS （CP ） BEGIN IF CP=‘1’ THEN Q<=D; END IF; END PROCESS; END test; 上升沿D触发器描述
上升沿D触发器描述 6O TAX+plus II- d: \studyid reg2-[d reg2. scf-FavefornEditorl 回冈 A MAKtplus II file edit yiew Node Assign Utilities Options indow Help 口②舀回△囫郾B郾囚囚為圖画露理雷眼食 A Ref 0.Ons 中|Tme:lns Interval: 6.0 0 Or Name 100Ons 200 Ons 300 0ns 400 Ons 500 Ons 6000ns 700 Ons 800 Ons 900 Ons 1.0 在系統可编程技术 G Microsoft PowerP 有dMA+ plus II-d mk16:35
上升沿D触发器描述
下降沿D触发器描述 方法一:使用信号属性函数 LIBRARY IEEE USE IEEESTD LOGIC 1164.ALL; ENTITY D reg Is PORT,CP: IN STD LOGIC Q: OUTSTD LOGIC); END D reg; ARCHITECTURE test OF D reg Is BEGIN PROCESS(CP) BEGIN IF(CPEVENT AND CP=0)THEN <=D END PROCESS END test
下降沿D触发器描述 方法一：使用信号属性函数 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(CP) BEGIN IF (CP’EVENT AND CP=‘0’) THEN Q<=D; END PROCESS; END test;
下降沿D触发器描述 方法二:使用WAI语句 LIBRARY IEEE. USE IEEESTD LOGIC 1164.ALL: ENTITY D reg Is PORTD, CP: IN STD LOGIC: Q: OUT STD LOGIC); END D reg ARCHITECTURE test OFD reg Is BEGIN PROCESS BEGIN WAIT UNTIL CP=0’; END PROCESS END test;
方法二：使用WAIT 语句 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS BEGIN WAIT UNTIL CP=‘0’; Q<=D; END PROCESS; END test; 下降沿D触发器描述
方法三:使用下降沿检测函数 LIBRARY IEEE: USE IEEESTD LOGIC 1164.ALL; 下降沿 ENTITY D reg Is PORTOD, CP: IN STD LOGIC; Q: OUT STD LOGIC) END D reg D触发器描述 ARCHITECTURE test OFd reg Is BEGIN PROCESS(P) BEGIN IF(falling edge(cp))THEN Q<=D END IF. END PROCESS END test:
方法三：使用下降沿检测函数 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(cp) BEGIN IF (falling_edge(cp)) THEN Q<=D; END IF; END PROCESS; END test; 下降沿D触发器描述
