￡ⅫNX° Writing Efficient Testbenches ONESOUT out STD LOGIC VECTOR(6 DOWNTo 0) TENSOUT out STD LOGIC VECTOR (6 DOWNTO 0) END COMPONENT SIGNAL CLK: STD LOGIC SIGNAL RESET. STD LOG SIGNAL STRTSTOP STD LOGICi IGNAL TENTHSOUT STD LOGIC VECTOR (9 SIGNAL ONESOUT: STD LOGIC VECTOR (6 D 0) SIGNAL TENSOUT STD LOGIC VECTOR (6 DC constant ClockPeriod: Time 60 ns §igna td BEGIN UU乎 PORT MAP CLK =>C RESET = RESET STRTSTOP = STRTSTOP TENTHSOUT = TENTHSOUT ONE SOUT = ONE SOUT TENSOUT = TENSOUT stimulus: PROCESS gir et startstop <= '1 wait for 240 ns reset<=′0′; startstop <=0 wait for 5000 nsi startstop <=1 wait for 8125 ns wait for 500 ns startstop<=1′; reset <=/1, As; Na for 875 reset <=/0 wait for 700 n startstop <=0 it for 550 n end timur it for 100 nsi wait for (Clock CLK < not ClKi nd loop; check ult variable tmptenthsout: std logic vector(9 downto 0) variable 1: line; www.xilinx.com XAPP199(v1.0)June11,2001 1-800-255-777812 www.xilinx.com XAPP199 (v1.0) June 11, 2001 1-800-255-7778 Writing Efficient Testbenches R ONESOUT : out STD_LOGIC_VECTOR (6 DOWNTO 0); TENSOUT : out STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; SIGNAL CLK : STD_LOGIC; SIGNAL RESET : STD_LOGIC; SIGNAL STRTSTOP : STD_LOGIC; SIGNAL TENTHSOUT : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL ONESOUT : STD_LOGIC_VECTOR (6 DOWNTO 0); SIGNAL TENSOUT : STD_LOGIC_VECTOR (6 DOWNTO 0); constant ClockPeriod : Time := 60 ns; FILE RESULTS: TEXT IS OUT "results.txt"; signal i: std_logic; BEGIN UUT : stopwatch PORT MAP ( CLK => CLK, RESET => RESET, STRTSTOP => STRTSTOP, TENTHSOUT => TENTHSOUT, ONESOUT => ONESOUT, TENSOUT => TENSOUT ); stimulus: PROCESS begin reset <= ’1’; strtstop <= ’1’; wait for 240 ns; reset <= ’0’; strtstop <= ’0’; wait for 5000 ns; strtstop <= ’1’; wait for 8125 ns; strtstop <= ’0’; wait for 500 ns; strtstop <= ’1’; wait for 875 ns; reset <= ’1’; wait for 375 ns; reset <= ’0’; wait for 700 ns; strtstop <= ’0’; wait for 550 ns; strtstop <= ’1’; end process stimulus; clock: process begin clk <= ’1’; wait for 100 ns; loop wait for (ClockPeriod / 2); CLK <= not CLK; end loop; end process clock; check_results : process variable tmptenthsout: std_logic_vector(9 downto 0); variable l: line;