Writing Efficient Testbenches ￡ⅫL|NX If the simulation succeeds, the following information is shown on the terminal screen Modelsim SE PLUS 5. 5a File Edit Design View Project Run Compare Macro Options Window Help 电岛厂画剑! vsSM14〉run23000ns Beginning Simulation. Pattern#t 0 time 1950. WE=0; Address=0: Data=00: Expected Q=xx Actual Q=xx Pattern# 1 time 2950: WE=1: Address=0; Data=01: Expected Q=01: Actual Q=01 t Pattern#t Pattern# 3 time 4950. WE=1: Address=2; Data=04: Expected Q=04: Actual 0=04 4 time 5950. WE=1: Address=3: Data=08: Expected Q=08: Actual Q=08 #Pattern't 5 time 6950. WE=1: Address=4; Data=10: Expected g-=10:Actual Q-10 Pattern# 6 time 7950: WE=1: Address=5: Data=20: Expected Q=20: Actual Q=20 f Pattern# 7 time 8950: WE=1: Address=6: Data=40: Expected Q=40: Actual Q=40 Pattern# 8 time 9950: WE=1: Address=7: Data=80: Expected Q=80: Actual Q=80 Pattern# 9 time 10950: WE=0: Address=0; Data=07: Expected Q=01: Actual Q=0 Pattern# 10 time 11950. WE=0: Address=1; Data=08: Expected Q=02: Actual Q=02 #Patterntt 11 time 12950 WE=0; Address=2: Data=09: Expected Q=04: Actual Q-0 Pattern# 12 time 13950 WE=0: Address=3: Data=10: Expected 0=08: Actual Q=08 #Pattern# 13 time 14950: WE=0; Address=4: Data=11: Expected Q=10; Actual 0=10 Patten# 4 time 15950 WE=0: Address=5; Data=12: Expected Q=20; Actual Q=20 Pattern#t 15 time 16950: WE=0: Address=6 Data=13: Expected Q=40: Actual Q=40 Pattem# 16 time 17950: WE=0: Address=7: Data=14: Expected Q=80: Actual Q=80 Pattern#t 17 time 18950: WE-1: Address=0: Data=aa; Expected @=aa; Actual Q=aa f Pattern 8 time 19950. WE=0: Address=0: Data=55: Expected Q=aa; Actual Q=a Pattern# 19 time 20950: WE=1: Address=0; Data=55: Expected Q=55: Actual Q=55 f Pattern#t O time 21950 WE=0: Address=0: Data=aa; Expected Q=55: Actual Q=55 Good End of good simulation #** Note: Finish projects/appnotes/testbenches/ ver example/test, v 112) Time: 22950 ns Iteration: 0 Instance: /test Break at F: /projects/appnotes/testbenches/ ver example/test. v line 112 s|M15 Now 22,950 ns Delta: sim: /test Figure 3: Verilog Example Verification VHDL Example In VHDL, a vector file contains expected results. The VHDL textio package is used to read data from the vector file, and to display error messages. This testbench instantiates the stopwatch design in VHDL L工 BRARY IEEE USE IEEE std logic 1164.all L工 BRARY leee UsE工EEE. STD LOGIC TEXT工0.ALL; USE STD. TEXTIO. ALL; ENTITY testbench END testbench ARCHITECTURE testbench arch of testbench IS COMPONENT stopwatch PORT CLK. in STD LOGIC RESET in STD LOGIC STRTSTOP in STD LOGIC TENTHSOUT: out STD LOGIC VECTOR(9 DOWNTo 0) XAPP199(v10)June11,2001 www.xilinx.com 1-800-255-7778Writing Efficient Testbenches XAPP199 (v1.0) June 11, 2001 www.xilinx.com 11 1-800-255-7778 R If the simulation succeeds, the following information is shown on the terminal screen: VHDL Example In VHDL, a vector file contains expected results. The VHDL textio package is used to read data from the vector file, and to display error messages. This testbench instantiates the stopwatch design in VHDL. LIBRARY IEEE; USE IEEE.std_logic_1164.all; LIBRARY ieee; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY testbench IS END testbench; ARCHITECTURE testbench_arch OF testbench IS COMPONENT stopwatch PORT ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; STRTSTOP : in STD_LOGIC; TENTHSOUT : out STD_LOGIC_VECTOR (9 DOWNTO 0); Figure 3: Verilog Example Verification