￡ⅫNX° Writing Efficient Testbenches #550 tbstrtstop 1 / simulation must be halted inside an initial statement //#100000$stop; end integer errors //1 // Block below compares the expected vs. actual results // at every negative clock edge /////1/11/ @(posedge bclk begi f (thstrtstop) begin errors =01 for (i=l; i < cycles; i =1 1 b bclk) result at nege Display ("Time d ns: TBSTRTSTOP=b; Reset=h: Expected Tenthsout=b: Actual Tenthsout=b", Sstime, tbstrtstop, tbresetr Data in t[il tbtenthsout) if( tbtenthsout Data in t[i] begin Display -ERROR. A mismatch has occurred errors= errors 1 en Sdisplay("simulation finished Successfully. " else if (errors >1) Sdisplay ("0d ERROR! See log above for details. ",errors)i Sdisplay("ERROR! See log above for details. ")i #100 sstop; endmodul This simple, self-checking testbench design can be ported to any test case-of course, expected-output values and signal names must be modified for reuse. If a check is not needed at each clock edge, the for- loop can be modified as needed www.xilinx.com XAPP199(v1.0)June11,2001 1-800-255-777810 www.xilinx.com XAPP199 (v1.0) June 11, 2001 1-800-255-7778 Writing Efficient Testbenches R #550 tbstrtstop = 1; // ///////////////////////////////////////////////////// // simulation must be halted inside an initial statement // ///////////////////////////////////////////////////// // #100000 $stop; end integer i,errors; /////////////////////////////////////////////////////////////////// /////////////// // Block below compares the expected vs. actual results // at every negative clock edge. /////////////////////////////////////////////////////////////////// /////////////// always @ (posedge tbclk) begin if (tbstrtstop) begin i = 0; errors = 0; end else begin for (i = 1; i <= cycles; i = i + 1) begin @(negedge tbclk) // check result at negedge $display("Time%d ns; TBSTRTSTOP=%b; Reset=%h; Expected TenthsOut=%b; Actual TenthsOut=%b", $stime, tbstrtstop, tbreset, Data_in_t[i], tbtenthsout); if ( tbtenthsout !== Data_in_t[i] ) begin $display(" ------ERROR. A mismatch has occurred-----"); errors = errors + 1; end end if (errors == 0) $display("Simulation finished Successfully."); else if (errors > 1) $display("%0d ERROR! See log above for details.",errors); else $display("ERROR! See log above for details."); #100 $stop; end end endmodule This simple, self-checking testbench design can be ported to any test case—of course, expected-output values and signal names must be modified for reuse. If a check is not needed at each clock edge, the for-loop can be modified as needed