Writing Efficient Testbenches ￡ⅫL|NX Data in t[5]=10′b1111101111; Data in t[6]=10′b1111011111 Data in t[7]=10′b1110111111; Data in t[8]=10′b1101111111 Data in t[10]=10′b0111111111 Data in t[11]=10′b1111111110; Data in t[12]=10′b1111111110 Data in t[13]=10′b1111111101; t[14]=10′b1111111011 Data in t[15]=10′b1111110111 Data in t[16]=10′b1111101111 Data_int[17]=10′b1111011111 Data in t[18]=10′b1110111111 t[19]=10′b1101111111 Data in t[20]=10′b1011111111 Data in t[21]=10′b0111111111; Data in t[22]=10′b1111111110 Data in t[23]=10′b1111111110 Data in t[24]=10′b1111111101 Data in t[25]=10′b1111111011 ign glbl GSR= GS initial begin GSR =1 / Wait till Global Reset Finished / Create the clock ial begin bclk 7/ Wait till Global Reset Finished, then cycle clock #100 forever #60 bclk bclk itial begin //////1 // Initialize All Input Ports tb 1 //////1 // Apply Design stimulus #240tb #5000 tbstrtstop #8125 tbstrtstop =0 #875tb #700 tbstrtstop 0 XAPP199(v10)June11,2001 www.xilinx.com 1-800-255-7778Writing Efficient Testbenches XAPP199 (v1.0) June 11, 2001 www.xilinx.com 9 1-800-255-7778 R Data_in_t[5] =10’b1111101111; Data_in_t[6] =10’b1111011111; Data_in_t[7] =10’b1110111111; Data_in_t[8] =10’b1101111111; Data_in_t[9] =10’b1011111111; Data_in_t[10]=10’b0111111111; Data_in_t[11]=10’b1111111110; Data_in_t[12]=10’b1111111110; Data_in_t[13]=10’b1111111101; Data_in_t[14]=10’b1111111011; Data_in_t[15]=10’b1111110111; Data_in_t[16]=10’b1111101111; Data_in_t[17]=10’b1111011111; Data_in_t[18]=10’b1110111111; Data_in_t[19]=10’b1101111111; Data_in_t[20]=10’b1011111111; Data_in_t[21]=10’b0111111111; Data_in_t[22]=10’b1111111110; Data_in_t[23]=10’b1111111110; Data_in_t[24]=10’b1111111101; Data_in_t[25]=10’b1111111011; end reg GSR; assign glbl.GSR = GSR; initial begin GSR = 1; // /////////////////////////////// // Wait till Global Reset Finished // /////////////////////////////// #100 GSR = 0; end // //////////////// // Create the clock // //////////////// initial begin tbclk = 0; // Wait till Global Reset Finished, then cycle clock #100 forever #60 tbclk = ~tbclk; end initial begin // ////////////////////////// // Initialize All Input Ports // ////////////////////////// tbreset = 1; tbstrtstop = 1; // ///////////////////// // Apply Design Stimulus // ///////////////////// #240 tbreset = 0; tbstrtstop = 0; #5000 tbstrtstop = 1; #8125 tbstrtstop = 0; #500 tbstrtstop = 1; #875 tbreset = 1; #375 tbreset = 0; #700 tbstrtstop = 0;