Clock Distribution(Yawn) Clock Distribution(Yawn The distribution of clocks throughout a design has received considerable atten- tion with the increase in logic speed Common-or-garden personal computers have bus speeds of 66 MHz, and processor clocks run at 300 MHz or greater. In this article we're concerned more with the possible pitfalls in the synchronous logic itself, not with the production of decent clocks. However, for completeness here are the important parameters necessary for a good clock distribution sys tem design Skew Minimization Clock skew is the variation in time of the clock's active transition being detected by different devices within a system. Skew must be kept to a mini- mum to ensure that setup and hold times are not violated at any one device Methods for managing skew include equal-length traces, zero-delay PLL based buffers, and additional logic for extending hold times The clock's waveform must be as clean and deterministic as possible. Tech- niques used to guarantee consistent clock behavior include transmission line termination, ground-bounce minimization, and the use of identical clock driv The Ten Commandments of Excellent DesignClock Distribution (Yawn) 4 The Ten Commandments of Excellent Design Clock Distribution (Yawn) The distribution of clocks throughout a design has received considerable atten￾tion with the increase in logic speed. Common-or-garden personal computers have bus speeds of 66 MHz, and processor clocks run at 300 MHz or greater. In this article we’re concerned more with the possible pitfalls in the synchronous logic itself, not with the production of decent clocks. However, for completeness, here are the important parameters necessary for a good clock distribution sys￾tem design: • Skew Minimization Clock skew is the variation in time of the clock’s active transition being detected by different devices within a system. Skew must be kept to a mini￾mum to ensure that setup and hold times are not violated at any one device. Methods for managing skew include equal-length traces, zero-delay PLL￾based buffers, and additional logic for extending hold times. • Clock Fidelity The clock’s waveform must be as clean and deterministic as possible. Tech￾niques used to guarantee consistent clock behavior include transmission line termination, ground-bounce minimization, and the use of identical clock driv￾ers