Digital Systems 101 the clock. When the rising edge occurs, the registers propagate the logic levels at their d inputs to their Q outputs Logic T D FIGURE1. Simple Example of a Synchronous Circuit In Figure 1, two important timing parameters are defined Setup Time-Tsu Setup time is the time that the D input to a register must be valid before the clock transitions Hold Time-Th Hold time is the period that the d input to a register must be maintained valid after the clock has transitioned If the setup or hold time parameters are violated terrible things happen. We'll discuss this later in the section on synchronization The Ten Commandments of Excellent DesignDigital Systems 101 The Ten Commandments of Excellent Design 3 the clock. When the rising edge occurs, the registers propagate the logic levels at their D inputs to their Q outputs. FIGURE 1. Simple Example of a Synchronous Circuit In Figure 1, two important timing parameters are defined: • Setup Time—Tsu Setup time is the time that the D input to a register must be valid before the clock transitions. • Hold Time—Th Hold time is the period that the D input to a register must be maintained valid after the clock has transitioned. If the setup or hold time parameters are violated terrible things happen. We’ll discuss this later in the section on synchronization. D Clock Combinatorial Q Logic Inputs Output Clock D Q Th Tsu