use ieee std logic arith all entity vadd is port(a, b: in std logic vector( 7 downto 0); c: in std lo s: out std logic vector(8 downto 0)); end vadd: architecture rtl of vadd is signal d: std logic vector(0 to O); d(0<=c; s<=(O'& unsigned(a))+unsigned(b)+unsigned(d) end rtI 注意:由于 unsigned()函数只针对数组,因此不能将c直 接变化,必须先将其写为数组信号;此外,为了使s的数据 宽度能够与右端运算匹配,应先将a的宽度扩展到8位 例p453表5-608位乘法器的设计 数据流设计 use ieee std logic 1164. all; use ieee std logic arith. all entity vmul8x8i is port(x,y: in std logic vector( 7 downto 0) p: out std logic vector(15 downto O)) end vmul8x8i architecture rtl of vmul 8i is p<=unsigned(x)*unsigned(y); nd rtIuse ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity vadd is port (a,b: in std_logic_vector( 7 downto 0 ); c : in std_logic; s : out std_logic_vector(8 downto 0)); end vadd; architecture rtl of vadd is signal d: std_logic_vector(0 to 0); begin d(0)<= c; s <= ('0' & unsigned(a)) +unsigned(b)+unsigned(d); end rtl; 注意：由于 unsigned（）函数只针对数组，因此不能将 c 直 接变化，必须先将其写为数组信号；此外，为了使 s 的数据 宽度能够与右端运算匹配，应先将 a 的宽度扩展到 8 位。 例 p.453 表 5-60 8 位乘法器的设计 数据流设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity vmul8x8i is port (x,y: in std_logic_vector( 7 downto 0 ); p : out std_logic_vector (15 downto 0)); end vmul8x8i; architecture rtl of vmul8x8i is begin p <= unsigned(x)*unsigned(y); end rtl;