/96 ■ Systolic architectures have a space-time representation where each node is mapped to a certain processing element(PE)and is scheduled at a particular time instance. ■ Systolic design methodology maps an N- dimensional DG to a lower dimensional systolic architecture. Mapping of N-dimensional DG to (N-1) dimensional systolic array is considered in this chapter. 2021年2月 42021年2月 4  Systolic architectures have a space-time representation where each node is mapped to a certain processing element (PE) and is scheduled at a particular time instance.  Systolic design methodology maps an N￾dimensional DG to a lower dimensional systolic architecture.  Mapping of N-dimensional DG to (N-1) dimensional systolic array is considered in this chapter