How do l implement this within EAB library ieee if (clIk'event and clk='1)then when state01101 = if(seral in ='1)then use ieee std logic 1164 all case present state is present state < state011011; package your own type is when idle = if(serial in present state < idle type t state is(idle, state0, state0l, state011 present state <=st state0110. state01101 when state011011 = present state <= idle < idle when others = present state < idle state011011) ena case end your own type hen state 1)then end if, library ieee staten end if, end process, use ieee std logic 1164. all e process(present state) use work. your own type. all Entity sth is if (present state =state011011)then when state01 in="1") 1 port (clk, serial in, reset: in std logic present match: out std logic) match <=0 end sth nd if, present end proces architecture body_ sth of stmh is end if end body signal present state: t state, when state011 O)then egin present e<=sta 110; process(clk, serial in, present state) presen state < idle end if if (reset ='1)then when state011(> if(serial_in=)then present state <=idle present _s te <=stateol pyright 1997 Altera Corporation present state < idle 2/22/2021P4 favaraCopyright © 1997 Altera Corporation 2/22/2021 P.4 How do I implement this within EAB library ieee; use ieee.std_logic_1164.all; package your_own_type is type t_state is (idle,state0,state01,state011, state0110,state01101, state011011); end your_own_type; library ieee; use ieee.std_logic_1164.all; use work.your_own_type.all; Entity stmh is port (clk, serial_in, reset : in std_logic; match : out std_logic); end stmh; architecture body_stmh of stmh is signal present_state : t_state; begin process(clk,serial_in, present_state) begin if (reset = '1') then present_state <= idle; else when state01101 => if (serial_in = '1') then present_state <= state011011; else present_state <= idle; end if; when state011011 => present_state <= idle; when others => present_state <= idle; end case; end if; end if; end process; process(present_state) begin if (present_state = state011011) then match <= '1'; else match <= '0'; end if; end process; end body_stmh; if (clk'event and clk='1') then case present_state is when idle => if (serial_in = '0') then present_state <= state0; else present_state <= idle; end if; when state0 => if (serial_in = '1') then present_state <= state01; else present_state <= idle; end if; when state01 => if (serial_in = '1') then present_state <= state011; else present_state <= idle; end if; when state011 => if (serial_in = '0') then present_state <= state0110; else present_state <= idle; end if; when state0110 => if (serial_in = '1') then present_state <= state01101; else present_state <= idle; end if;