小m FIGURE 81.17 Gate-level logic circuit for binary to seven-segment hexadecimal character generator. The lumped delays provide an approximate measure of circuit speed or settling time(the time it takes an output ignal to become stable after the input signals have become stable) Figure 81.17 illustrates the gate-level method(random logic method) of implementing a binary to seven- segment hexadecimal character generator suitable for driving a seven-segment common cathode led display like the one in Fig. 81.18. The propagation delays of logic circuits are seldom shown on logic circuit diagrams; however, these delays are inherent in each logic element and must be considered in systems designs. This gate-level combinational logic circuit converts the binary input code 0000 though 11l1 represented on the signal inputs D(MSB)C B A(LSB)to the binary code on the signal outputs OA through OG. These outputs generate the hexadecimal haracters 0 through F when applied to a seven-segment common cathode LEd display. Each of the signal lines D, D, through A, A must be capable of driving the number of gate inputs shown in the brackets(fan-out requirement) to both the high-level and low-level required voltages. The output equations for the circuit in Fig 81.17 are the minimum sum of products(SOP)equations for the 1s of the functions OA though OG, respectively, represented by the truth table in Table 81.4 A more efficient way(in terms of package count)to implement the same combinational logic function would be to use a medium-scale integration(MSI)4-to 16-line decoder with gates as illustrated in Fig. 81.19. The tildes are used as in-line symbols for the logical complements of Do through D15 as recommended by ieee. e 2000 by CRC Press LLC© 2000 by CRC Press LLC The lumped delays provide an approximate measure of circuit speed or settling time (the time it takes an output signal to become stable after the input signals have become stable). Figure 81.17 illustrates the gate-level method (random logic method) of implementing a binary to seven￾segment hexadecimal character generator suitable for driving a seven-segment common cathode LED display like the one in Fig. 81.18. The propagation delays of logic circuits are seldom shown on logic circuit diagrams; however, these delays are inherent in each logic element and must be considered in systems designs. This gate-level combinational logic circuit converts the binary input code 0000 though 1111 represented on the signal inputs D(MSB) C B A(LSB) to the binary code on the signal outputs OA through OG. These outputs generate the hexadecimal characters 0 through F when applied to a seven-segment common cathode LED display. Each of the signal lines D, , through A, must be capable of driving the number of gate inputs shown in the brackets (fan-out requirement) to both the high-level and low-level required voltages. The output equations for the circuit in Fig. 81.17 are the minimum sum of products (SOP) equations for the 1’s of the functions OA though OG, respectively, represented by the truth table in Table 81.4. A more efficient way (in terms of package count) to implement the same combinational logic function would be to use a medium-scale integration (MSI) 4- to 16-1ine decoder with gates as illustrated in Fig. 81.19. The tildes are used as in-line symbols for the logical complements of D0 through D15 as recommended by IEEE. FIGURE 81.17 Gate-level logic circuit for binary to seven-segment hexadecimal character generator. D A