Q0 FIGURE 81. 18 Seven-segment common cathode led display TABLE814 Truth Table for Binary to Seven-Segment Hexadecimal Character Generator Seven-Segment Output DCB AOA O OD OE OF OG Display Character 0 0 00011110000 00 1010101010101 10110111111010 010001010l11l 23456789Abcd 0 The decoder circuit in Fig. 81.19 requires only 8 IC packages compared to the gate-level circuit in Fig. 81.17 which requires 18 IC packa ges. Functio onally, both circuits perform the same. The output equations for the circuit in Fig. 81.19 are the canonical or standard SoP equations for the 0s of the functions OA though OG, respectively, represented by the truth table(Table 81.4). The gates shown in Fig. 81. 19 with more than four inputs are eight-input NAND gates with each unused input tied to Vac via a pull-up resistor (not shown on the logic diagram). An even more efficient way to implement the same combinational logic function would be to utilize part of a simple programmable read only memory(PROM)circuit such as the 27$19 fuse programmable PROM in Fig 81.20. An equivalent architectural gate structure for a portion of the PROM is shown in Fig. 81.21. The Xs in Fig. 81.21 represent fuses that are left intact after programming the device. The code for programming the PROM or generating the truth table of the function can be read either from the truth table(Table 81.4)or directly from each line of the circuit diagram in Fig. 81.21(expressed in hexadecimal: 7E, 30, 6D, 79, 33, 5B, 5F, 70, 7E, 7B, 77, IF, 4E, 3D, 4F, and 47)beginning with the first line, which represents binary input 0000, e 2000 by CRC Press LLC© 2000 by CRC Press LLC The decoder circuit in Fig. 81.19 requires only 8 IC packages compared to the gate-level circuit in Fig. 81.17 which requires 18 IC packages. Functionally, both circuits perform the same. The output equations for the circuit in Fig. 81.19 are the canonical or standard SOP equations for the 0’s of the functions OA though OG, respectively, represented by the truth table (Table 81.4). The gates shown in Fig. 81.19 with more than four inputs are eight-input NAND gates with each unused input tied to VCC via a pull-up resistor (not shown on the logic diagram). An even more efficient way to implement the same combinational logic function would be to utilize part of a simple programmable read only memory (PROM) circuit such as the 27S19 fuse programmable PROM in Fig. 81.20. An equivalent architectural gate structure for a portion of the PROM is shown in Fig. 81.21. The X’s in Fig. 81.21 represent fuses that are left intact after programming the device. The code for programming the PROM or generating the truth table of the function can be read either from the truth table (Table 81.4) or directly from each line of the circuit diagram in Fig. 81.21 (expressed in hexadecimal: 7E, 30, 6D, 79, 33, 5B, 5F, 70, 7F, 7B, 77, 1F, 4E, 3D, 4F, and 47) beginning with the first line, which represents binary input 0000, FIGURE 81.18 Seven-segment common cathode LED display. TABLE 81.4 Truth Table for Binary to Seven-Segment Hexadecimal Character Generator Binary Inputs Seven-Segment Outputs D C B A OA OB OC OD OE OF OG Displayed Characters 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 2 0 0 1 1 1 1 1 1 0 0 1 3 0 1 0 0 0 1 1 0 0 1 1 4 0 1 0 1 1 0 1 1 0 1 1 5 0 1 1 0 1 0 1 1 1 1 1 6 0 1 1 1 1 1 1 0 0 0 0 7 1 0 0 0 1 1 1 1 1 1 1 8 1 0 0 1 1 1 1 1 0 1 1 9 1 0 1 0 1 1 1 0 1 1 1 A 1 0 1 1 0 0 1 1 1 1 1 b 1 1 0 0 1 0 0 1 1 1 0 C 1 1 0 1 0 1 1 1 1 0 1 d 1 1 1 0 1 0 0 1 1 1 1 E 1 1 1 1 1 0 0 0 1 1 1 F