K述列 4.1多路选择器VHDL指述 4.1.12选1多路选择器的ⅤHDL描述 【例4-1】 ENTITY mux21a IS PoR(a,b:工NB工T; 工NB工T; Y:OUB工T); END ENTITY mux21a ARCHITECTURE one oF mux21a IS BEG工N a WHEN S E 0 ELSE END ARCHITECTURE one;KX 康芯科技 4.1 多路选择器VHDL描述 4.1.1 2选1多路选择器的VHDL描述 【例4-1】 ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN y <= a WHEN s = '0' ELSE b ; END ARCHITECTURE one ;