VHDL大小写不敏感 eqcomp4 vhd 文件名和实体 名一致 库 eqcomp4 is a four bit equality comparator Library ieee 包 use IEEE. td logic 1164.a f: 实体一 entity egcomp4is port(a, b: in std logic vector(3 downto 0) 每行;结尾 equal out std logic) end egcomp4 关键字end后跟 实体名 构造体一 architecture dataflow of eqcomp44is begin 关键字 begin equal <-=1 when a=b else 0 End dataflow 关键字end后跟 构造体名--eqcomp4 is a four bit equality comparator Library IEEE; use IEEE.std_logic_1164.all; entity eqcomp4 is port(a, b:in std_logic_vector(3 downto 0); equal :out std_logic); end eqcomp4; architecture dataflow of eqcomp4 is begin equal <= ‘1’ when a=b else ‘0’; End dataflow; VHDL 大小写不敏感 eqcomp4.vhd 包 实体 构造体 文件名和实体 名一致 每行；结尾 关键字begin 关键字end后跟 实体名 关键字end后跟 构造体名 库