FLEX 10K FLEX 10K Device Block Diagram OFPGA: CMOS SRAM-based PLDs .10,000 to 250,000 logical gates .Up to 20 EABs, 2048bits per EAB O MultiVolt 1O: drive and be driven by 3.3/5V devices 目自三 9In-Circuit Reconfigurablity via external configuration devices, MCU, or JTAG Q Built-in JTAG boundary-scan test circuitry FLEX 10K Device Block Diagram EX10 K Logical Element(日 ◆逻辑资源LAB- Logic Array Block ◆LE ●8 LEs per LAB ◆存储器资源EAB- Embeded Array Block ●2048 bits per EAB eRoM、RAM、F|FO、 DPRAM ◆O资源|OE- O Element ◆互连线资源一 FastTrack FLEX 10K LE FLEX 10K LE ◆4输入LUT,实现任意组合逻辑 ◆每个LE能同时驱动 ◆DFF ● Local Inter Connect oClock Enable .FastTrack InterConnect ●Asyn.cear& Preset .Clock. Clear Preset come from ◆每个LE提供进位链和级联链 > Global Signals ●联接LAB内所有LE General lo pins >Any internal logic8 46 FLEX 10K ‹FPGA: CMOS SRAM-based PLDs z10,000 to 250,000 logical gates zUp to 20 EABs, 2048bits per EAB ‹MultiVolt I/O: drive and be driven by 3.3/5V devices ‹In-Circuit Reconfigurablity via external configuration devices, MCU, or JTAG ‹Built-in JTAG boundary-scan test circuitry 47 FLEX 10K Device Block Diagram 48 FLEX 10K Device Block Diagram ‹逻辑资源LAB—Logic Array Block z8LEs per LAB ‹存储器资源EAB—Embeded Array Block z2048bits per EAB zROM、RAM、FIFO、DPRAM ‹I/O资源IOE—I/O Element ‹互连线资源—FastTrack 49 FLEX 10K Logical Element FLEX 10K Logical Element (LE) ‹LE 50 FLEX 10K LEC ‹4输入LUT，实现任意组合逻辑 ‹DFF zClock Enable zAsyn. Clear & Preset zClock, Clear & Preset come from ¾Global Signals ¾General I/O pins ¾Any internal logic 51 FLEX 10K LE ‹每个LE能同时驱动 zLocal InterConnect zFastTrack InterConnect ‹每个LE提供进位链和级联链 z联接LAB内所有LE