或 libraryieee, use ieeestd logic_1164.all; use ieee std_logicunsigned.all entity halt sub 1s port(a, b:in std_ logic, dout, cout: outsid logic) end half sub architecture one ofhalf sub is signal temp: std _logic_vector(1 downto 0 begin temp<=("0′&a)-b; dout<=temp(o); cout<=temp(1) end one或 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity half_sub is port(a,b:in std_logic; dout, cout: outstd_logic); end half_sub; architecture one of half_sub is signal temp: std_logic_vector(1 downto 0); begin temp<=(‘0’&a )-b; dout<=temp(0); cout<=temp(1); end one;