●采用原理图输入法 半减器原理图编辑 ●采用文本编辑法 library ieee; useieee.std_logic_1164. all; entity half subis port(a, b:in std _ logic, dout, cout: out std _ logic); end half sub architecture one ofhalf sub is b gin dout<=axor b: cout<=not a and b: end one.⚫采用原理图输入法 XOR inst NOT inst1 AND2 inst2 VCC a INPUT VCC b INPUT OUTPUT dout OUTPUT cout 半减器原理图编辑 ⚫采用文本编辑法 library ieee; use ieee.std_logic_1164.all; entity half_sub is port(a,b:in std_logic; dout, cout: outstd_logic); end half_sub; architecture one of half_sub is begin dout<=a xor b; cout<=not a and b; end one;