SEQ+ Hardware Memory ■ Still sequential implementation Reorder PC stage to put at beginning PC Stage Task is to select Pc for current instruction Decode ■ Based on resu|ts computed by previous rite bac instruction Processor State Fetch increment a Pc is no longer stored in register But, can determine Pc based on other stored formation 5 Processor– 5 – Processor Instruction memory PC increment CC ALU Data memory PC rB dstE dstM ALUA ALUB Mem. control Addr srcA srcB read write ALU fun. Fetch Decode Execute Memory Write back data out Register file A B ME Register file A B ME Bch dstE dstM srcA srcB icode ifun rA pIcode pBch pValM pValC pValP PC valC valP valA valB Data valE valM PC SEQ+ Hardware ◼ Still sequential implementation ◼ Reorder PC stage to put at beginning PC Stage ◼ Task is to select PC for current instruction ◼ Based on results computed by previous instruction Processor State ◼ PC is no longer stored in register ◼ But, can determine PC based on other stored information