architecture mixt of kbencoder is signal a0 std logic vector(2 downto 0) signal d: std logic vector(2 downto 0); signal k: std logic vector(7 downto 0) signal m: std logic vector(7 downto 0); component encoder is port(i: in std logic vector (7 downto 0) el: in std I a: out std logic vector(2 downto O)) nen ul: encoder port map(i, e, a0) d(o)= not a0(0); d (1)= not a0(1), d (2)<=not a0(2) with d select k<= o111lll1" when 000 10111111" when001 "11011111" when 010 11101111 when01l 11110111"when"100 "11111011"when "101" "11111101" when"110" "11111110" when"111" "11111111"when othe m(O)=k(0) xnor i(0): m(1)=k(1)xnor i() m(2)<=k(2) xnor I(2);m(3)=k(3) xnor I(3) m(4)<=k(4) Xnor I(4);m(5)<=k(5) Xnor I(5) m(6<=k(6) Xnor I(6),m(7)<=k(7) Xnor I(7) u2: encoder port map(m, e, b) end mixtarchitecture mixt of kbencoder is signal a0:std_logic_vector(2 downto 0); signal d: std_logic_vector(2 downto 0); signal k: std_logic_vector(7 downto 0); signal m: std_logic_vector(7 downto 0); component kencoder is port (i: in std_logic_vector (7 downto 0); el: in std_logic; a: out std_logic_vector(2 downto 0)); end component ; begin u1: kencoder port map (i,e, a0 ); d(0)<= not a0(0); d(1)<= not a0(1); d(2)<= not a0(2); a<=a0; with d select k<= "01111111" when "000", "10111111" when "001", "11011111" when "010", "11101111" when "011", "11110111" when "100", "11111011" when "101", "11111101" when "110", "11111110" when "111", "11111111" when others; m(0)<= k(0) xnor i(0); m(1)<= k(1) xnor i(1); m(2)<= k(2) xnor i(2); m(3)<= k(3) xnor i(3); m(4)<= k(4) xnor i(4); m(5)<= k(5) xnor i(5); m(6)<= k(6) xnor i(6); m(7)<= k(7) xnor i(7); u2: kencoder port map (m,e,b); end mixt;