National semiconductor June 1989 DM54LS75/DM74LS75 Quad Latches General Description as present at the data input at the N ge for bin ar informat on between processing units and ata time the trans tiom ture d is retained at the Q output un A ture complementary O and O outputs e high, and the Q output will follow the data input as long as from a 4-bit latch, and are available in 16pin packages. the enable remains high. When the enable goes low, Connection Diagram Function Table(Each Latch) Enable H- High Level, L -Low Level. x-Don't Care Op- The Level of a Before the High-to-Low Transition of ENABLE Order Number DM54LS75J. DM54LS7 DM7ALS75M See Ns Package Number J16A, M16A, N16A or W16A Logic Diagram(Each Latch) TLFA8374-2TL/F/6374 DM54LS75/DM74LS75 Quad Latches June 1989 DM54LS75/DM74LS75 Quad Latches General Description These latches are ideally suited for use as temporary stor￾age for binary information between processing units and in￾put/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is high, and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occured) is retained at the Q output until the enable is permitted to go high. These latches feature complementary Q and Q outputs from a 4-bit latch, and are available in 16-pin packages. Connection Diagram Dual-In-Line Package TL/F/6374 –1 Order Number DM54LS75J, DM54LS75W, DM74LS75M or DM74LS75N See NS Package Number J16A, M16A, N16A or W16A Function Table (Each Latch) Inputs Outputs D Enable Q Q L H LH H H HL XLQ0 Q0 H e High Level, L e Low Level, X e Don’t Care Q0 e The Level of Q Before the High-to-Low Transition of ENABLE Logic Diagram (Each Latch) TL/F/6374 –2 C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A