VpD D Q6 Ds D4 Q4 LE 20 19 18 16 15 14 13 12 11 D D OE OE OE OE 10 OE Qo Do D D, D3 Q GND Output Latch D Q H-high level,L-low level Enable Enable Output Qo level of output before steady-state input L H H H condtons were establshed. L H Z-high impedance L L JX L Qo X 2、CMOS八D-Latch：74HC373 VDD Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE OE Q0 D0 D1 Q1 Q2 D2 D3 Q4 GND Q D