PtGATE N-TYPE CHANNEL P+ GATE FIGURE 24.1 、 PT GATE PtGATE N-TYPE CHANNEL FIGURE 24.2 FIGURE 24. 3 for the case of VGs =0 as Vs increases In Fig. 24. 4(a)the situation is shown for the case of Vns=0 in which the JFET is fully""and there is a uniform channel from source to drain. This is at point A on the Ins vs. Vos curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of gs(on), and the drain-to- source resistance is correspondingly at its minimum value of Tas (on). Now let's consider the case of Vns=+l V, shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still VGs=0. The gate-to-channel bias voltage at the drain end is VGp= VGs-Vos=-1 V, so the depletion region will be wider at the drain end of the channel than at the source end. the channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance ga and, correspondingly, an increase in the channel resistance ras. So the slope of the Ips vs. Vos curve that corresponds to the channel conductance will be smaller at Vns=1 V than it was at Vns =0, as shown at point B on the Ips vS. Vrs curve of Fig. 24.5 In Fig. 24.4(c)the situation for Vns =+2 V is shown. The gate-to-channel bias voltage at the source end is still VGs =0, but the gate-to-channel bias voltage at the drain end is now VGp=VGs-Vps=-2V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance ga and, correspondingly, an increase in the channel resistance ras. So the slope of the Ips vs. Vos urve will be smaller at Vns=2V than it was at Vns=1 V, as shown at point Con the Ips vS Vns curve of Fig. 24 In Fig. 24. 4(d)the situation for Vps =+3 V is shown, and this corresponds to point d on the IIs vs. Vps curve of Fig. 24.5 When Vns=+4 V, the gate-to-channel bias voltage will be VGD=Vo-Vns =0-4V=-4 V= Vp. As a result the channel is now pinched off at the drain end but is still wide open at the source end since VGs=0,as nown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain -to-source current i can still continue to flow this is not at all the same situation as for the case of Vas= Vp, where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and Ips is reduced to essentially zero. The situation for Vns=+4 V=-Vp is shown at point E on the Ips curve of Fig. 24.5 For Vps >+4 V, the current essentially saturates and doesnt increase much with further increases in Vps. As Vps increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases Tas. This increase in ras essentially counterbalances the increase in Vps such that Ips does not increase much This region of the Ins vS. Vps curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be sed as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of VGs=0 is called the drain saturation current, Ipss(the third subscript S c 2000 by CRC Press LLC© 2000 by CRC Press LLC for the case of VGS = 0 as VDS increases. In Fig. 24.4(a) the situation is shown for the case of VDS = 0 in which the JFET is fully “on” and there is a uniform channel from source to drain. This is at point A on the IDS vs. VDS curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of gds (on), and the drain-to￾source resistance is correspondingly at its minimum value of rds (on). Now let’s consider the case of VDS = +1 V, as shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still VGS = 0. The gate-to-channel bias voltage at the drain end is VGD = VGS –VDS = –1 V, so the depletion region will be wider at the drain end of the channel than at the source end. The channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance gds and, correspondingly, an increase in the channel resistance rds . So the slope of the IDS vs. VDS curve that corresponds to the channel conductance will be smaller at VDS = 1 V than it was at VDS = 0, as shown at point B on the IDS vs. VDS curve of Fig. 24.5. In Fig. 24.4(c) the situation for VDS = +2 V is shown. The gate-to-channel bias voltage at the source end is still VGS = 0, but the gate-to-channel bias voltage at the drain end is now VGD = VGS – VDS = –2 V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance gds and, correspondingly, an increase in the channel resistance rds . So the slope of the IDS vs. VDS curve will be smaller at VDS = 2 V than it was at VDS = 1 V, as shown at point C on the IDS vs.VDS curve of Fig. 24.5. In Fig. 24.4(d) the situation for VDS = +3 V is shown, and this corresponds to point D on the IDS vs. VDS curve of Fig. 24.5. When VDS = +4 V, the gate-to-channel bias voltage will be VGD = VGS – VDS = 0 – 4 V = –4 V = VP . As a result the channel is now pinched off at the drain end but is still wide open at the source end since VGS = 0, as shown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain-to-source current IDS can still continue to flow. This is not at all the same situation as for the case of VGS = VP , where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and IDS is reduced to essentially zero. The situation for VDS = +4 V = –VP is shown at point E on the IDS vs. VDS curve of Fig. 24.5. For VDS > +4 V, the current essentially saturates and doesn’t increase much with further increases in VDS . As VDS increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases rds . This increase in rds essentially counterbalances the increase in VDS such that IDS does not increase much. This region of the IDS vs. VDS curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be used as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of VGS = 0 is called the drain saturation current, IDSS (the third subscript S FIGURE 24.1 FIGURE 24.2 FIGURE 24.3