Note that will not se all of the address and da on the IS6ILV25616AL chip for your 32x8 memory:connect the unneeded ports to0 in your VHDL entity. SRAM port name DE2 pin name A17-0 SRAM_ADDR17-0 SRAM_DQ150 SRAM_CE SRAM.O SRAMInN Table 3.DE2 pin names for the SRAM chip. 2.Compile the circuit and download it into the FPGA chip. 3.Test the functionality of your design by reading and writing values to several different memory locations. Part V The sram block in fig o 1 hee a ein ides the address for both read and write orerodp portatvthedror operation o he lngp 1 create a ne ouartus ii proieet for voureircuit to generate the desired memory module onen the megaWiz ard Plug-in Manager and select again the altsyncram LPM in the storage category.On Page 1 ofthe Wizard HowhalBehneeapotingone write port (simple du l-port mode)in the category called y0 do Pages Mix g-Write fo Single Input Clock RAM.This setting specifies that it does not matter whether the memory outputs the new data being written,or the old data previously stored,in the case that the write and read addresses are the same Page 7 of the Wizard is displaved in Figure 5.It makes use of a feature that allows the memory module the circuit is programm ed in the FPGA chip.As shown in the figure he memory con E da e th and me ra create specify some data values to be stored in the memory.Finish the Wiard and then examine the generated memory module in the file ramlpm.vhd. 6 Note that you will not use all of the address and data ports on the IS61LV25616AL chip for your 32 x 8 memory; connect the unneeded ports to 0 in your VHDL entity. SRAM port name DE2 pin name A17−0 SRAM ADDR17−0 I/O15−0 SRAM DQ15−0 CE SRAM CE N OE SRAM OE N W E SRAM WE N UB SRAM UB N LB SRAM LB N Table 3. DE2 pin names for the SRAM chip. 2. Compile the circuit and download it into the FPGA chip. 3. Test the functionality of your design by reading and writing values to several different memory locations. Part V The SRAM block in Figure 1 has a single port that provides the address for both read and write operations. For this part you will create a different type of memory module, in which there is one port for supplying the address for a read operation, and a separate port that gives the address for a write operation. Perform the following steps. 1. Create a new Quartus II project for your circuit. To generate the desired memory module open the MegaWiz￾ard Plug-in Manager and select again the altsyncram LPM in the storage category. On Page 1 of the Wizard choose the setting With one read port and one write port (simple dual-port mode) in the category called How will you be using the altsyncram?. Advance through Pages 2 to 5 and make the same choices as in Part II. On Page 6 choose the setting I don’t care in the category Mixed Port Read-During-Write for Single Input Clock RAM. This setting specifies that it does not matter whether the memory outputs the new data being written, or the old data previously stored, in the case that the write and read addresses are the same. Page 7 of the Wizard is displayed in Figure 5. It makes use of a feature that allows the memory module to be loaded with initial data when the circuit is programmed into the FPGA chip. As shown in the figure, choose the setting Yes, use this file for the memory content data, and specify the filename ramlpm.mif. To learn about the format of a memory initialization file (MIF), see the Quartus II Help. You will need to create this file and specify some data values to be stored in the memory. Finish the Wizard and then examine the generated memory module in the file ramlpm.vhd. 6