Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 Clock Division Factor Byte 321 00000000 POWER ON VALUE [0 X1010POWER ONVALUE DMA BURST K DIVISION F DMA ENABLE RESERVED AUTO RELOAD SOF-ONLY interrupt mode INTERRUPT PIN MODE ENDPOINT INDEX 4 INTERRUPT ENABLE Clock Division Factor The value indicates clock division ENDPOINT INDEX 5 INTERRUPT ENABLE factor for CLKOUT. The output sv863 frequency is 48 MHZ/(N+1) where N is the Clock Division Factor. The reset DMA Burst Selects the burst length for DMA operation value is 11. This will produce the output frequency of 4 MHz which can then be programmed up(or down) by 01 Burst (4 cycle)DMA the user. The minimum value is one giving the range of frequency from 4 11 Burst(16 cycle) DMA to 24 MHz. the minimum value of n DMA Enable is zERo giving a maximum frequency Writing a"1 to this bit will start DMA operation through the assertion of DMREQ of 48 MHz. The maximum value of n The main endpoint buffer needs to be full is ELEVEN givi (for DMA Read) or empty(for DMA Write) equency of 4 MHz. The PDIUSBD12 before DMREQ will be asserted. In a single lesign ensures no glitching during cle DMA mode, the dmreq is y change The prog grammed deactivated upon receiving DMACK N In value will not be changed by a bus burst mode DMA, the dMREQ is deactivated after the number of burst is SET TO ONE This bit needs to be set to 1 prior to exhausted. It is then asserted again for the any DMA read or DMA write lext burst. This process continues until peration. This bit should always be OT_ N is asserted together with DMACK_ N set to 1 after power. It is zero afte and either rd n or wr n which will reset his bit to o and terminate the dma operation. The DMA operation can also be SOF-ONLY interrupt mode Setting this bit to 1 will cause the terminated by writing a 0 to this bit terrupt line to be interrupted due to Start of Frame clock (SOF)ONLY, DMA Direction This bit determines the direction of data flow regardless of the setting of luring a DMA transfer. A1 means external pin-interrupt mode, bit 5 of setDMA. mared memory to PDIUSBD12 (DM Write); a 0 means PDIUSBD12 to the Command FBh Auto reload When this bit is set to 1, the DMA operation will automatically restart. Data Read/write 1 byte The set DMA command is followed by one data write/read to/from Interrupt Pin Mode A0 signifies a normal interrupt pin mode the DMA configuration register. where interrupt is generated as a logical OR of all the bits in the interrupt registers. A" DMA Configuration register ignifies that the interrupt will occur when During DMA operation, the two-byte buffer header(status and byte Start of Frame clock(SoF) is seen on the length information) is not transferred to/from the local CPU. This upstream USB bus. The other normal allows dma data to be continuous and not interleaved by chunks of interrupts are still active these headers For DMA read operation, the header will be skipped by the PDIUSBD12. See Read Buffer command For DMA write Endpoint Index 4 operation, the header will be automatically added by the Interrupt Enable A 1 allows for interrupt to be generated PDIUSBD12. This provides for a clean and simple DMA data whenever the int buffer contains a valid packet. ly turned off for DMA Endpoint Index 5 Interrupt Enable A 1 allows for interrupt to be generated whenever the endpoint buffer is validated (see the Validate Buffer command) orally turned off for DMA operatic reduce unnecessary CPU servicingPhilips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 10 Clock Division Factor Byte 76 5 4 3 2 1 1 1 0 0 0 X X 1 0 POWER ON VALUE CLOCK DIVISION FACTOR RESERVED SV00862 SET_TO_ONE SOF-ONLY interrupt mode Clock Division Factor The value indicates clock division factor for CLKOUT. The output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up (or down) by the user. The minimum value is one giving the range of frequency from 4 to 24 MHz. The minimum value of N is ZERO giving a maximum frequency of 48 MHz. The maximum value of N is ELEVEN giving a minimum frequency of 4 MHz. The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. SET_TO_ONE This bit needs to be set to 1 prior to any DMA read or DMA write operation. This bit should always be set to 1 after power. It is zero after power–on reset. SOF-ONLY interrupt mode Setting this bit to 1 will cause the interrupt line to be interrupted due to Start of Frame clock (SOF) ONLY, regardless of the setting of pin-interrupt mode, bit 5 of setDMA. Set DMA Command : FBh Data : Read/Write 1 byte The set DMA command is followed by one data write/read to/from the DMA configuration register. DMA Configuration register During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operation, the header will be skipped by the PDIUSBD12. See Read Buffer command. For DMA write operation, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer. POWER ON VALUE INTERRUPT PIN MODE ENDPOINT INDEX 4 INTERRUPT ENABLE ENDPOINT INDEX 5 INTERRUPT ENABLE 76 54 32 0 1 0 0 0 0 0 0 0 0 DMA ENABLE DMA DIRECTION AUTO RELOAD DMA BURST SV00863 DMA Burst Selects the burst length for DMA operation: 00 Single cycle DMA 01 Burst (4 cycle) DMA 10 Burst (8 cycle) DMA 11 Burst (16 cycle) DMA DMA Enable Writing a ‘1’ to this bit will start DMA operation through the assertion of DMREQ. The main endpoint buffer needs to be full (for DMA Read) or empty (for DMA Write) before DMREQ will be asserted. In a single cycle DMA mode, the DMREQ is deactivated upon receiving DMACK_N. In burst mode DMA, the DMREQ is deactivated after the number of burst is exhausted. It is then asserted again for the next burst. This process continues until EOT_N is asserted together with DMACK_N and either RD_N or WR_N which will reset this bit to ‘0’ and terminate the DMA operation. The DMA operation can also be terminated by writing a ‘0’ to this bit. DMA Direction This bit determines the direction of data flow during a DMA transfer. A ‘1’ means external shared memory to PDIUSBD12 (DMA Write); a ‘0’ means PDIUSBD12 to the external shared memory (DMA Read). Auto Reload When this bit is set to ‘1’, the DMA operation will automatically restart. Interrupt Pin Mode A ‘0’ signifies a normal interrupt pin mode where interrupt is generated as a logical OR of all the bits in the interrupt registers. A ‘1’ signifies that the interrupt will occur when Start of Frame clock (SOF) is seen on the upstream USB bus. The other normal interrupts are still active. Endpoint Index 4 Interrupt Enable A ‘1’ allows for interrupt to be generated whenever the endpoint buffer contains a valid packet. Normally turned off for DMA operation to reduce unnecessary CPU servicing. Endpoint Index 5 Interrupt Enable A ‘1’ allows for interrupt to be generated whenever the endpoint buffer is validated (see the Validate Buffer command). Normally turned off for DMA operation to reduce unnecessary CPU servicing