tO Example on MSI Cache Coherence Request Processor P1 Processor p2 BU Memory State Addr value State Addr Value Proc Addr Action Addr value P1: Write 10 to A1 P1 A1 Wr Miss A1 15 MA110 P1: Read A1(Hit) M A1 10 P2: Read A1 P2 A1 Rd miss SA110 P1 A1 Wr Back A1 10 s A1 10 P2 A1 Transfer P2: Write 20 to a1 P2 A1 Invalidate A110 MA120 A110 P2: Write 40 to A2 MA240 A225 Assume that a1 and a2 map to same cache block Initial cache state is invalid 2021/2/1 计算机体系结构Example on MSI Cache Coherence 2021/2/1 计算机体系结构 7 • Assume that A1 and A2 map to same cache block • Initial cache state is invalid