MSI Snoopy Cache Coherence protocol Request Source State Transition Action and Explanation Read Hit Processor Shared or Modified Normal Hit: Read data in private data cache (no transaction Read Miss Processor Invalid Shared Normal Miss: Place read miss on bus, change state Read Miss Processor Shared Replace block Place read miss on bus Read Miss Processor Modified> Shared Write-Back block, Place read miss on bus, change state rite Hit Processor Modified Normal Hit: Write data in private data cache (no transaction) Write Hit Processor Shared,Modified Coherence: Place invalidate on bus(no data), change state Write Miss Processor Invalid, Modified Normal Miss: Place write miss on bus, change state Write Miss Processor Shared >Modified Replace block: Place write miss on bus, change state Write Miss Processor Modified Write-Back block, Place write miss on bus Read Miss Bus Shared Serve read miss from shared cache or memory Read miss Bus Modified Shared Coherence: Write-Back Serve read miss, change state Invalidate Bus Shared >Invalid Coherence: Invalidate shared block in other private caches Write Miss Bus Shared Invalid Coherence: Invalidate shared block in other private caches Write miss Bus Modified Invalid Coherence: Write-Back Serve write miss, InvalidateMSI Snoopy Cache Coherence Protocol 2021/2/1 计算机体系结构 6