O MSI Snoopy Cache Coherence Protocol CPU read hit Write miss for this block Invalidate for Shared Invalid CPU read this block Place read mlss on bus"(read only) nvalid Shared CPU CPU CPU write miss read mIss Place read miss on bus Write miss for this block Read mIss for this block Cache state transitions Cache state transitions based Exclusive based on requests from CPU Exclusive on requests from the bus (read/write) CPU write miss Write-back cache block Place wrlte mIss on bus 当所访问的块的最新数据在某个私有 Cache时,在读写 CPU write hit 失效时,数据的提供者是拥有该块数据的私有 Cache CPU read hit 动作: Write-back block; abort memory access 2021/2/1 计算机体系结构MSI Snoopy Cache Coherence Protocol 2021/2/1 计算机体系结构 5 当所访问的块的最新数据在某个私有Cache时，在读写 失效时，数据的提供者是拥有该块数据的私有Cache。 动作：Write-back block; abort memory access