Description Levels of HDL Testbenches Formal documentation, 业 to communicate structural dataflow behavioral with other designers (sequential) Components and Concurrent interconnects statements 水 Subsetmostsuitable Registers State machines for synthesis一 Decoders HDL for Specification HDL for Simulation Test and verify a design (Feed it), to input to a simulator HDL for Synthesis (For Real Hardware) Realize and Iterate a digital logic design,to input to a synthesizer 2021/1/13 ASIC Design,by Yan BoASIC Design, by Yan Bo 9 Description Levels of HDL HDL for Specification HDL for Simulation HDL for Synthesis (For Real Hardware) Formal documentation, to communicate with other designers Test and verify a design (Feed it), to input to a simulator Realize and Iterate a digital logic design, to input to a synthesizer 2021/1/13 Components and interconnects structural behavioral (sequential) Registers State machines Decoders Subset most suitable for synthesis Testbenches dataflow Concurrent statements