Components of a Verilog Module module Timing Specifications (Port List) Port Data Type Circuit Subprograms Declarations Declarations Functionality Instantiation task input net Continuous Procedural function output register Assignment Blocks System Tasks always inout parameter assign block Compiler Directives initial block 2021/1/13 ASIC Design,by Yan Bo 10ASIC Design, by Yan Bo Components of a Verilog Module module (Port List) Port Declarations input output inout Data Type Declarations net register parameter Circuit Functionality Timing Specifications Continuous Assignment assign Procedural Blocks always block Subprograms task function System Tasks Compiler Directives Instantiation initial block 2021/1/13 10