Implementing Pipeline Control Figure 4.68 P351 wicode valE dstE dstM icode B咄EaA dstE dstM E dstM bubble control E icode ifun valC valA valB dste dstM srcA srcB d srcB srcB D bul D_stall icode ifun F_stall predIC Combinational logic generates pipeline control signals Action occurs at start of following cycle Processor– 16 – Processor Implementing Pipeline Control ◼ Combinational logic generates pipeline control signals ◼ Action occurs at start of following cycle E M W F D CC rB srcA srcB icode valE valM dstE dstM icode Bch valE valA dstE dstM icode ifun valC valA valB dstE dstM srcA srcB icode ifun rA valC valP predPC d_srcB d_srcA e_Bch D_icode E_icode M_icode E_dstM Pipe control logic D_bubble D_stall E_bubble F_stall Figure 4.68 P351