Initial Version of Pipeline Control bool f stall Conditions for a load/use hazard Stalling at fetch while ret passes through pipeline\srcB E icode ini IMRMOVL, IPOPL && E dstM in i d srcA, d IReT in( D icode,E icode, M icode )i bool d stall Conditions for a load/use hazard E icode in IMRMOVL, IPOPL &&e dstM in d srcA, d srcb i bool d bubble Mispredicted branch (E icode IUXX &&!e Bch)I I talling at fetch while ret passes through pipeline Iret in( D icode, E icode, M icode F bool E bubble Mispredicted branch (E icode = IuxX &&!e Bch) Load/use hazard E icode in[ IMRMoVL, IPOPl]&&e dstm in[ d srcA, d srcB)i Processor– 17 – Processor Initial Version of Pipeline Control bool F_stall = # Conditions for a load/use hazard E_icode in { IMRMOVL, IPOPL } && E_dstM in { d_srcA, d_srcB } || # Stalling at fetch while ret passes through pipeline IRET in { D_icode, E_icode, M_icode }; bool D_stall = # Conditions for a load/use hazard E_icode in { IMRMOVL, IPOPL } && E_dstM in { d_srcA, d_srcB }; bool D_bubble = # Mispredicted branch (E_icode == IJXX && !e_Bch) || # Stalling at fetch while ret passes through pipeline IRET in { D_icode, E_icode, M_icode }; bool E_bubble = # Mispredicted branch (E_icode == IJXX && !e_Bch) || # Load/use hazard E_icode in { IMRMOVL, IPOPL } && E_dstM in { d_srcA, d_srcB};