Timing Simulation Output Nam value 100ns 200.ns 300.Ons 400.ns cIra lK l「「「「「 d3 o dO It get worst What is going on? Engineer Design problem or Altera Device Problem But .... It works with 74xX TtL logic and fail with altera device. it must be altera device problem bBRA Copyright 1997 Altera Corporation 9/12/97Copyright © 1997 Altera Corporation 9/12/97 Timing Simulation Output It get worst !!! What is going on ? Engineer Design problem or Altera Device Problem ? But ..... It works with 74xx TTL logic and fail with Altera Device, it must be Altera Device Problem