Asynchronous Circuit Design a Mainly use Combinational Logic to do the decoding Address decoder Fifo/Ram Read or Write pulse a The output logic does not have any relationship with any clocking signal a Usually the Decoding Glitch can be monitored at the output signal Copyright 1997 Altera Corporation 9/12/97Copyright © 1997 Altera Corporation 9/12/97 Asynchronous Circuit Design ◼ Mainly use Combinational Logic to do the decoding – Address decoder – Fifo/Ram Read or Write pulse ◼ The output logic does not have any relationship with any clocking signal ◼ Usually the Decoding Glitch can be monitored at the output signal