2、16位锁存器regl6b MAX+plus II-f: \ dh\mp2 \eda tech_ app \e6_2\andarith-reg16b whd-Text EditorI R MAX+plus I Ele Edt Templates Assign Utilties options window Help ×」 library ieee; use ieee std logic 1164.all entity regl6b is port(clk, clr: in std logic d: in std logic vector(8 downto o) g: out std logic vector (15 downto 0))i end regl6bi rchitecture art of regl6b is signal rls: std logic vector (15 downto 0)i begi process(clk, clr) egl ifc1r=!1 then r16s<="0000000000000000"; elsif clkfevent and clk=1 then r16s(6 downto o<=r16s(7 downto 1) r16s(15 downto 7)<=d; end ifi end process a=r16s end art I Line 1[ Col 16 INSI9 2、16位锁存器reg16b