Writing Efficient Testbenches ￡ⅫL|NX port (clock in std logici reset in st d: in std logici sel in std logic vector (1 downto 0) d logic hiftreg out std logic vector(4 downto 0)) nd componenti signal clock, reset, load: std logic signal shiftreg, data: std logic vector(4 downto 0) constant ClockPeriod: TIME 50 ns n UUT shift reg port map (clock = clock, reset = reset, load = load, data = dat shiftreg = shiftreg)i process begin clock < not clock after (clockPeriod / 2) end process process begin data<="00000 it for 200 nsi reset<=!0′ data<="00001 wait for 100 nsi se1<="01 1oad<=!0′ 1<="10"; it for 1000 hitecture test r The VHDL testbench above is similar in functionality to the Verilog testbench shown previously, with the exception of a command to echo the output to the terminal In VHDL, the std textio package is used to display information to the terminal, and this will be covered in the next section Automatic g the verification of testbench results is recommended, particularly for large Verification utomation reduces the time required to check a design for correctness, and human error Several methods are commonly used to automate testbench verification Database Comparisons. First, a database file containing expected output(a"golden vector" file)is created. Then, simulation outputs are captured and compared to the reference vectors in the golden vector file( the unix diff utility can be used to compare the ASCll database files). However, since pointers from output to input files are not provided, a disadvantage of this method is the difficulty of tracing an incorrect output to the source of the error 2. Waveform Comparison Waveform comparisons can be performed automatically or manually. The automatic method employs a testbench comparator to compare a golden waveform against the testbench output waveform. The Xilinx HDL Bencher tool can be XAPP199(v10)June11,2001 www.xilinx.com 1-800-255-7778Writing Efficient Testbenches XAPP199 (v1.0) June 11, 2001 www.xilinx.com 7 1-800-255-7778 R port (clock : in std_logic; reset : in std_logic; load : in std_logic; sel : in std_logic_vector(1 downto 0); data : in std_logic_vector(4 downto 0); shiftreg : out std_logic_vector(4 downto 0)); end component; signal clock, reset, load: std_logic; signal shiftreg, data: std_logic_vector(4 downto 0); signal sel: std_logic_vector(1 downto 0); constant ClockPeriod : TIME := 50 ns; begin UUT : shift_reg port map (clock => clock, reset => reset, load => load, data => data, shiftreg => shiftreg); process begin clock <= not clock after (ClockPeriod / 2); end process; process begin reset <= ’1’; data <= "00000"; load <= ’0’; set <= "00"; wait for 200 ns; reset <= ’0’; load <= ’1’; wait for 200 ns; data <= "00001"; wait for 100 ns; sel <= "01"; load <= ’0’; wait for 200 ns; sel <= "10"; wait for 1000 ns; end process; end architecture test_reg; The VHDL testbench above is similar in functionality to the Verilog testbench shown previously, with the exception of a command to echo the output to the terminal. In VHDL, the std_textio package is used to display information to the terminal, and this will be covered in the next section. Automatic Verification Automating the verification of testbench results is recommended, particularly for larger designs. Automation reduces the time required to check a design for correctness, and minimizes human error. Several methods are commonly used to automate testbench verification: 1. Database Comparisons. First, a database file containing expected output (a “golden vector” file) is created. Then, simulation outputs are captured and compared to the reference vectors in the golden vector file (the unix diff utility can be used to compare the ASCII database files). However, since pointers from output to input files are not provided, a disadvantage of this method is the difficulty of tracing an incorrect output to the source of the error. 2. Waveform Comparison. Waveform comparisons can be performed automatically or manually. The automatic method employs a testbench comparator to compare a golden waveform against the testbench output waveform. The Xilinx HDL Bencher tool can be