￡ⅫNX° Writing Efficient Testbenches reg reset / declaration of signals wire [4: 0] shiftregi reg [4:01 datai reg [1: 0] sel // instantiation of the shift reg design below shift reg dut( clock (clock) load (load) reset (reset) shiftreg (shiftreg e1(se1)) //this process block sets up the free running clock tial b lock =0 #50 clock clock end initial begin// this process block specifies the stimulus reset = 1i dat 5′b00000 load se1=2′b00; #200 data=5′b00001 oad = 0: #200 2′b10 #1000 ssto d initial begin// this process block pipes the ASCII results to the Stimeformat(-9, l,ns",12)i Sdisplay (" Time clk Rst Ld SftRg Data Sel")i Monitor("暑t悬b各b暑b暑b暑b各b",Srea1time clock, reset, load, shiftreg, data, sel) dimodule The testbench, above, instantiates the design, sets up the clock, then provides the stimuli. All process blocks start at simulation time zero and are concurrent. The pound sign(#) specifies the delay before the next stimulus is applied. The Sstop command instructs the simulator to stop testbench simulation(all testbenches should contain a stop command). Finally, the Smonitor statement echoes the results in ASCll format to the screen or a piped text editor. Following is a VHDL testbench that instantiates and provides stimulus to the verilog shift VHDL Example: library IEEe entity testbench is end entity testbench architecture test reg of testbench is t re www.xilinx.com XAPP199(v1.0)June11,2001 1-800-255-77786 www.xilinx.com XAPP199 (v1.0) June 11, 2001 1-800-255-7778 Writing Efficient Testbenches R reg reset; // declaration of signals wire [4:0] shiftreg; reg [4:0] data; reg [1:0] sel; // instantiation of the shift_reg design below shift_reg dut(.clock (clock), .load (load), .reset (reset), .shiftreg (shiftreg), .data (data), .sel (sel)); //this process block sets up the free running clock initial begin clock = 0; forever #50 clock = ~clock; end initial begin// this process block specifies the stimulus. reset = 1; data = 5’b00000; load = 0; sel = 2’b00; #200 reset = 0; load = 1; #200 data = 5’b00001; #100 sel = 2’b01; load = 0; #200 sel = 2’b10; #1000 $stop; end initial begin// this process block pipes the ASCII results to the //terminal or text editor $timeformat(-9,1,"ns",12); $display(" Time Clk Rst Ld SftRg Data Sel"); $monitor("%t %b %b %b %b %b %b", $realtime, clock, reset, load, shiftreg, data, sel); end endmodule The testbench, above, instantiates the design, sets up the clock, then provides the stimuli. All process blocks start at simulation time zero and are concurrent. The pound sign (#) specifies the delay before the next stimulus is applied. The $stop command instructs the simulator to stop testbench simulation (all testbenches should contain a stop command). Finally, the $monitor statement echoes the results in ASCII format to the screen or a piped text editor. Following is a VHDL testbench that instantiates and provides stimulus to the Verilog shift register design above. VHDL Example: library IEEE; use IEEE.std_logic_1164.all; entity testbench is end entity testbench; architecture test_reg of testbench is component shift_reg is