Writing Efficient Testbenches ￡ⅫL|NX specifier formats the clock value in binary format. Verilog provides additional format-specifiers for example, %h is used for hexadecimal, %d for decimal, and %o for octal formats(consult a Verilog reference for a complete list of keywords and format specifiers) The formatted display results are shown in Figure 2 M ModelSin还E53d 口区 File Edit Design View Run Macro Options wi sG曲岛!群「100图系|刊 VSIM 11> run 200 ns Time Clk Rst Ld sftRg Data Sel #00ns010ww0000 500s110000000000000 1000ns01000000000000 1500ns1100000000 SIM 12> Now. 200 ns Delta: 2 sim: /testbench igure 2: Simulation Results Echoed to Terminal Simple Simple testbenches instantiate the user design then provide stimuli to it. Testbench output is Testbenches displayed graphically on the simulator's waveform window or as text sent to the users terminal r to a piped text file Below is a simple Verilog design representing a shift register module shift reg (clock, reset, load, sel, data, shiftreg) input clock, Input reset input load t[1:0]se1 input [4: 0] data output [4:0] shiftreg ys @(posedge clock) begin if (reset) shifty else if (load) shiftreg data (se1) 2 b00: shiftreg shiftreg 2′b01: shift hift <<1 2 b10: shiftreg shiftreg > 1 default shiftreg shiftreg endcase The following simple testbench examples instantiate the shift register design ilog Exampl module testbench; / declare testbench name eg cloc eg load XAPP199(v10)June11,2001 www.xilinx.com 1-800-255-7778Writing Efficient Testbenches XAPP199 (v1.0) June 11, 2001 www.xilinx.com 5 1-800-255-7778 R specifier formats the clock value in binary format. Verilog provides additional format-specifiers, for example, %h is used for hexadecimal, %d for decimal, and %o for octal formats (consult a Verilog reference for a complete list of keywords and format specifiers). The formatted display results are shown in Figure 2. Simple Testbenches Simple testbenches instantiate the user design, then provide stimuli to it. Testbench output is displayed graphically on the simulator's waveform window or as text sent to the user’s terminal or to a piped text file. Below is a simple Verilog design representing a shift register: module shift_reg (clock, reset, load, sel, data, shiftreg); input clock; input reset; input load; input [1:0] sel; input [4:0] data; output [4:0] shiftreg; reg [4:0] shiftreg; always @ (posedge clock) begin if (reset) shiftreg = 0; else if (load) shiftreg = data; else case (sel) 2’b00 : shiftreg = shiftreg; 2’b01 : shiftreg = shiftreg << 1; 2’b10 : shiftreg = shiftreg >> 1; default : shiftreg = shiftreg; endcase end endmodule The following simple testbench examples instantiate the shift register design. Verilog Example: module testbench; // declare testbench name reg clock; reg load; Figure 2: Simulation Results Echoed to Terminal