￡ⅫNX° Writing Efficient Testbenches e Time Stimulus Example VHDL-RELATIVE TIME Verilog- RELATIVE TIME Process (Clock) lways @(posedge clock Begin TB Count < TB Count 1 If rising edge(Clock)then initial begin TB Count < TB Count 1; f (TB Count <= 5) d g end process Secondstimulus: process begin oad =0: if(TB Count <=5) then Count upDn Reset Count upDn<=0′ begin Else Reset =07 Reset < Load<=1′; t UpDn Count upDn end process end Finalstimulus: process begin initial begin 1100")then Count UpDn <='0'i Count UpDn <=0; report "Terminal Count Display("Terminal Count d nd i end process end VHDL process blocks and verilog initial blocks are executed concurrently along with other process and initial blocks in the file. However, within each(process or initial) block, events are concurrent block at simulation time zero. Multiple blocks should be used to break up complex stimulus sequences into more readable and maintainable cod Display ing Results Displaying results is facilitated in Verilog by the Display and Monitor keywords. Altho VHDL does not have equivalent display-specific commands, it provides the std textio package, which allows file I/O redirection to the display terminal window (for an example of this technique see Self-Checking Testbenches, below) The following is a Verilog example in which values are displayed on the terminal screen // pipes the ASCII results to the terminal or text editor initial begin Monitor("暑t悬b旨b暑bb各b各b",$rea1time, lock, reset, load, shiftreg, data, sel) The Display keyword outputs quoted parenthetical text(. )to the terminal window. The Smonitor keyword works differently, since its output is event-driven. In the example, the Realtime variable(assigned by the user to the current simulation time) is used to trigger the display of values in the signal list. The signal list starts with the Realtime variable, and is followed by the names of other signals whose values are to be displayed(clock, reset, load, and others). The beginning" %keywords comprise a list of format specifiers, used to control ho each signal value in the signal list is formatted for display. The format list is positional-each format specifier is sequentially associated with a successive signal name in the signal list. For example, the %t specifier formats the displayed Realtime value in time format, and the first %b www.xilinx.com XAPP199(v1.0)June11,2001 1-800-255-77784 www.xilinx.com XAPP199 (v1.0) June 11, 2001 1-800-255-7778 Writing Efficient Testbenches R VHDL process blocks and Verilog initial blocks are executed concurrently along with other process and initial blocks in the file. However, within each (process or initial) block, events are scheduled sequentially, in the order written. This means that stimulus sequences begin in each concurrent block at simulation time zero. Multiple blocks should be used to break up complex stimulus sequences into more readable and maintainable code. Displaying Results Displaying results is facilitated in Verilog by the $display and $monitor keywords. Although VHDL does not have equivalent display-specific commands, it provides the std_textio package, which allows file I/O redirection to the display terminal window (for an example of this technique, see Self-Checking Testbenches, below). The following is a Verilog example in which values are displayed on the terminal screen: // pipes the ASCII results to the terminal or text editor initial begin $timeformat(-9,1,"ns",12); $display(" Time Clk Rst Ld SftRg Data Sel"); $monitor("%t %b %b %b %b %b %b", $realtime, clock, reset, load, shiftreg, data, sel); end The $display keyword outputs quoted parenthetical text (“...”) to the terminal window. The $monitor keyword works differently, since its output is event-driven. In the example, the $realtime variable (assigned by the user to the current simulation time) is used to trigger the display of values in the signal list. The signal list starts with the $realtime variable, and is followed by the names of other signals whose values are to be displayed (clock, reset, load, and others). The beginning “%” keywords comprise a list of format specifiers, used to control how each signal value in the signal list is formatted for display. The format list is positional—each format specifier is sequentially associated with a successive signal name in the signal list. For example, the %t specifier formats the displayed $realtime value in time format, and the first %b Table 3: Relative Time Stimulus Example VHDL-RELATIVE TIME Verilog-RELATIVE TIME Process (Clock) Begin If rising_edge(Clock) then TB_Count <= TB_Count + 1; end if; end process; SecondStimulus: process begin if (TB_Count <= 5) then Reset <= ’1’; Load <= ’0’; Count_UpDn <= ’0’; Else Reset <= ’0’; Load <= ‘1’; Count_UpDn <= ‘1’; end process; FinalStimulus: process begin if (Count = "1100") then Count_UpDn <= '0'; report "Terminal Count Reached, now counting down." end if; end process; always @ (posedge clock) TB_Count <= TB_Count + 1; initial begin if (TB_Count <= 5) begin Reset = 1; Load = 0; Count _UpDn = 0; end else begin Reset = 0; Load = 1; Count_UpDn = 1; end end initial begin if (Count == 1100) begin Count_UpDn <= 0; $display("Terminal Count Reached, now counting down."); end end