Writing Efficient Testbenches ￡ⅫL|NX C1ock<=1′; wait for (clockPeriod / 2) end processi // Declare a clock period constant Parameter ClockPeriod =10: / clock Generation method 1 initial begin end / clock Generation method 2 initial begin always #(clockPeriod /2)clock = -clocki Providing stimulus To obtain testbench verification results, stimulus must be provided to the DUT. Concurrent stimulus blocks are used in testbenches to provide the necessary stimuli. Two methods are employed: absolute-time stimulus and relative-time stimulus In the first method, simulation values are specified relative to simulation time zero. By comparison, relative-time stimulus supplies initial values, then waits for an event before retriggering the stimulus. Both methods can be combined in a testbench, according to the designer's needs Table 2 and Table 3 provide examples of absolute-time and relative-time stimuli, respectively, in VHDL and Verilog source code Table 2: Absolute Time Stimulus Example VHDL-ABSOLUTE TIME Verilog-ABSOLUTE TIME Mainstimulus: process begin initial begin Reset<=1′; Load<=′0′ Count UpDn <=0 wait for 100 ns #100 Reset =0 Reset<=0′; #20 Load 1 wait for 20 ns: #20 Count UpDn =li Load <=/1 end wait for 20 nsi end process; XAPP199(v10)June11,2001 www.xilinx.com 1-800-255-7778Writing Efficient Testbenches XAPP199 (v1.0) June 11, 2001 www.xilinx.com 3 1-800-255-7778 R wait for (ClockPeriod / 2) Clock <= ’1’; wait for (ClockPeriod / 2) Clock <= ’0’; end process; Verilog: // Declare a clock period constant. Parameter ClockPeriod = 10; // Clock Generation method 1: initial begin forever Clock = #(ClockPeriod / 2) ~ Clock; end // Clock Generation method 2: initial begin always #(ClockPeriod / 2) Clock = ~Clock; end Providing Stimulus To obtain testbench verification results, stimulus must be provided to the DUT. Concurrent stimulus blocks are used in testbenches to provide the necessary stimuli. Two methods are employed: absolute-time stimulus and relative-time stimulus. In the first method, simulation values are specified relative to simulation time zero. By comparison, relative-time stimulus supplies initial values, then waits for an event before retriggering the stimulus. Both methods can be combined in a testbench, according to the designer’s needs. Table 2 and Table 3 provide examples of absolute-time and relative-time stimuli, respectively, in VHDL and Verilog source code. Table 2: Absolute Time Stimulus Example VHDL-ABSOLUTE TIME Verilog-ABSOLUTE TIME MainStimulus: process begin Reset <= ’1’; Load <= ’0’; Count_UpDn <= ’0’; wait for 100 ns; Reset <= ’0’; wait for 20 ns; Load <= ’1’; wait for 20 ns; Count_UpDn <= ’1’; end process; initial begin Reset = 1; Load = 0; Count_UpDn = 0; #100 Reset = 0; #20 Load = 1; #20 Count_UpDn = 1; end