￡ⅫNX° Writing Efficient Testbenches languages, verification suites written in VHDL or Verilog can be reused in future designs Testbench Verification Flow Testbench Displays values Testbench Instantiates Design on Terminal and Provides stimulus Design Under Test Verify Result (DUT) on Waveform Testbench Checks for Correctness XAPP199_01042 Figure 1: HDL Verification Flow Using Testbenches Constructing Testbenches can be written in VHDL or Verilog. Since testbenches are used for simulation only, Testbenches they are not limited by semantic constraints that apply to rtl language subsets used in synthesis. Instead, all behavioral constructs can be used. Thus, testbenches can be written more generically, making them easier to maintain All testbenches contain the basic sections shown in Table 1. As mentioned above. testbenches typically contain additional functionality as well, such as the visual display of results on a terminal and built-in error detection Table 1: Sections Common to Testbenches VHDL Verilog Entity and Architecture Declaration Module declaration Signal Declaration Signal declaration Instantiation of Top-level Design Instantiation of Top-level Design Provide stimulus Provide stimulus The following examples show some constructs used frequently in testbenches Generating Clock Signa Designs that use system clocks to sequence logic must generate a clock Iterative clocks can easily be implemented in both VHDL and verilog source code. The following are VHDL and Verilog examples of clock generation: VHDL iod constant Constant ClockPeriod: TIME =10 ns Clock Generation method 1 clock < not clock after clockPeriod /2 Clock Generation method 2 GENERATE CLOCK: process www.xilinx.com XAPP199(v1.0)June11,2001 1-800-255-77782 www.xilinx.com XAPP199 (v1.0) June 11, 2001 1-800-255-7778 Writing Efficient Testbenches R languages, verification suites written in VHDL or Verilog can be reused in future designs without difficulty. Constructing Testbenches Testbenches can be written in VHDL or Verilog. Since testbenches are used for simulation only, they are not limited by semantic constraints that apply to RTL language subsets used in synthesis. Instead, all behavioral constructs can be used. Thus, testbenches can be written more generically, making them easier to maintain. All testbenches contain the basic sections shown in Table 1. As mentioned, above, testbenches typically contain additional functionality as well, such as the visual display of results on a terminal and built-in error detection. The following examples show some constructs used frequently in testbenches.: Generating Clock Signals Designs that use system clocks to sequence logic must generate a clock. Iterative clocks can easily be implemented in both VHDL and Verilog source code. The following are VHDL and Verilog examples of clock generation: VHDL: -- Declare a clock period constant. Constant ClockPeriod : TIME := 10 ns; -- Clock Generation method 1: Clock <= not Clock after ClockPeriod / 2; -- Clock Generation method 2: GENERATE CLOCK: process begin Figure 1: HDL Verification Flow Using Testbenches Testbench Verification Flow Testbench Instantiates Design and Provides Stimulus Design Under Test (DUT) Testbench Displays Values on Terminal Verify Result on Waveform Testbench Checks for Correctness XAPP199_01_042001 Table 1: Sections Common to Testbenches VHDL Verilog Entity and Architecture Declaration Module Declaration Signal Declaration Signal Declaration Instantiation of Top-level Design Instantiation of Top-level Design Provide Stimulus Provide Stimulus