esTc 设计中 Design Hierarchically-Multiple Design Files VHDL hierarchical design requires Component Declarations and Component Instantiations top. vhd entity-architecturetop" component“mid_a”, component“midb” mid a vhd mid b. vhd component“ bottom a entity-architecture"mid entity-architecture"mid b component“ bottom a component“ bottom b” bottom a vhd bottom b vhd entity-architecture"bottom_aLentity-architecture"bottom_b设计中心 Design Hierarchically - Multiple Design Files • VHDL hierarchical design requires Component Declarations and Component Instantiations top.vhd entity-architecture “top” component “mid_a” ，component “mid_b” mid_a. vhd entity-architecture “mid_a” component “bottom_a” mid_b. vhd entity-architecture “mid_b” component “bottom_a” component “bottom_b” bottom_a. vhd entity-architecture “bottom_a” bottom_b. vhd entity-architecture “bottom_b