Conventional DRAM organization dxw DRAM: dw total bits organized as d supercells of size w bits Figure 6.3 P459 16 8 DRAM chip cols 0 2 bits 0 addr i r memory controller supercell (to CPU) 8 bits data internal row buffer9 Conventional DRAM organization • d x w DRAM: – dw total bits organized as d supercells of size w bits cols rows 0 1 2 3 0 1 2 3 internal row buffer 16 x 8 DRAM chip addr data supercell (2,1) 2 bits / 8 bits / memory controller (to CPU) Figure 6.3 P459