Memory Hierarchy
1 Memory Hierarchy
Outline Random-Access Memory(RAM) Nonvolatile Memory Disk Storage Locality Memory hierarchy Suggested Reading: 6. 1, 6.2, 6.3 Nonvolatile:非易失的
2 Outline • Random-Access Memory (RAM) • Nonvolatile Memory • Disk Storage • Locality • Memory hierarchy • Suggested Reading: 6.1, 6.2, 6.3 Nonvolatile: 非易失的
6. 1 Storage Technologies
3 6.1 Storage Technologies
6. 1.1 Random-Access Memory
4 6.1.1 Random-Access Memory
Random-Access Memory (RAM) y features RAM is packaged as a chi Basic storage unit is a cell(one bit per ce Multiple raM chips form a memory
5 Random-Access Memory (RAM) • Key features – RAM is packaged as a chip. – Basic storage unit is a cell (one bit per cell). – Multiple RAM chips form a memory
Random-Access Memory (RAM) Static RAM (SRAM) Each cell stores bit with a six-transistor circuit Retains value indefinitely, as long as it is kept powered Relatively insensitive to disturbances such as electrical noise Faster and more expensive than dram
6 Random-Access Memory (RAM) • Static RAM (SRAM) – Each cell stores bit with a six-transistor circuit. – Retains value indefinitely, as long as it is kept powered. – Relatively insensitive to disturbances such as electrical noise. – Faster and more expensive than DRAM
Random-Access Memory (RAM) Dynamic RAM (DRam) Each cell stores bit with a capacitor and transistor Value must be refreshed every 10-100 ms Sensitive to disturbances Slower and cheaper than SRAM
7 Random-Access Memory (RAM) • Dynamic RAM (DRAM) – Each cell stores bit with a capacitor and transistor. – Value must be refreshed every 10-100 ms. – Sensitive to disturbances. – Slower and cheaper than SRAM
SRAM VS DRAM summary Figure 6.2 P458 T ran Access per bit time Persist? Sensitive? Cost Applications SRAM 6 1X No 100x cache memories DRAM 1 10X No Yes 1X Main memories frame buffers
8 SRAM vs DRAM summary Tran. Access per bit time Persist?Sensitive? Cost Applications SRAM 6 1X Yes No 100x cache memories DRAM 1 10X No Yes 1X Main memories, frame buffers Figure 6.2 P458
Conventional DRAM organization dxw DRAM: dw total bits organized as d supercells of size w bits Figure 6.3 P459 16 8 DRAM chip cols 0 2 bits 0 addr i r memory controller supercell (to CPU) 8 bits data internal row buffer
9 Conventional DRAM organization • d x w DRAM: – dw total bits organized as d supercells of size w bits cols rows 0 1 2 3 0 1 2 3 internal row buffer 16 x 8 DRAM chip addr data supercell (2,1) 2 bits / 8 bits / memory controller (to CPU) Figure 6.3 P459
Reading DRAM supercell (2, 1) Step 1(a): Row access strobe(ras)selects row 2 Step 1(b ) Row 2 copied from dram array to row buffer 16 8 DRAM chi cols 0 RAS =2 addr rows memory controller data row 2 Figure 6.4 (a) p460 internal row buffer
10 Reading DRAM supercell (2,1) • Step 1(a): Row access strobe (RAS) selects row 2. • Step 1(b): Row 2 copied from DRAM array to row buffer. RAS = 2 cols rows 0 1 2 3 0 1 2 3 internal row buffer 16 x 8 DRAM chip row 2 addr data 2 / 8 / memory controller Figure 6.4 (a) P460
