Processor Architecture Architecture (
Architecture (I) Processor Architecture
Goal Understand basic computer organization a Instruction set architecture Deeply explore the CPU working mechanism How the instruction is executed: sequential and pipeline version Help you programming a Fully understand how computer is organized and works will help you write more stable and efficient code Processor
– 2 – Processor Goal Understand basic computer organization ◼ Instruction set architecture Deeply explore the CPU working mechanism ◼ How the instruction is executed: sequential and pipeline version Help you programming ◼ Fully understand how computer is organized and works will help you write more stable and efficient code
CPU Design(Why?) It is interesting. Aid in understanding how the overall computer system works Many design hardware systems containing processors Maybe you will work on a processor design. Processor
– 3 – Processor CPU Design (Why?) It is interesting. Aid in understanding how the overall computer system works. Many design hardware systems containing processors. Maybe you will work on a processor design
CPU Design Instruction set architecture Logic design Sequential implementation Pipelining and initial pipelined implementation Making the pipeline work Modern processor design Processor
– 4 – Processor CPU Design Instruction set architecture Logic design Sequential implementation Pipelining and initial pipelined implementation Making the pipeline work Modern processor design
Suggested Reading Chap 4.1, 4.2 Processor
– 5 – Processor Suggested Reading - Chap 4.1, 4.2
Instruction Set Architecture #1 What is it Assem ble Language Abstraction Instruction Set Machine Language abstraction Architecture(ISA) What does it provide? a An abstraction of the real computer, hide the details of implementation The syntax of computer instructions The semantics of instructions ● The execution model Programmer-visible computer status Processor
– 6 – Processor Instruction Set Architecture #1 What is it ? ◼ Assemble Language Abstraction ◼ Machine Language Abstraction What does it provide? ◼ An abstraction of the real computer, hide the details of implementation ⚫ The syntax of computer instructions ⚫ The semantics of instructions ⚫ The execution model ⚫ Programmer-visible computer status Instruction Set Architecture (ISA)
Instruction Set Architecture #2 Assembly Language View ■ Processor state Application ● Registers, memory,… Program ■| nstructions Compiler OS addl,mov1,1ea1,… e How instructions are encoded as ISA bytes CPU Layer of Abstraction Design Above: how to program machine Circuit e Processor executes instructions Design In a sequence Chip a Below: what needs to be built Layout e Use tricks to make it run fast O E.g., execute multiple instructions simultaneously Processor
– 7 – Processor Instruction Set Architecture #2 Assembly Language View ◼ Processor state ⚫ Registers, memory, … ◼ Instructions ⚫ addl, movl, leal, … ⚫ How instructions are encoded as bytes Layer of Abstraction ◼ Above: how to program machine ⚫ Processor executes instructions in a sequence ◼ Below: what needs to be built ⚫ Use tricks to make it run fast ⚫ E.g., execute multiple instructions simultaneously ISA Compiler OS CPU Design Circuit Design Chip Layout Application Program
Instruction Set Architecture #3 isA define the processor family a Two main kind: risc and cisc RISC: SPARC, MIPS, PowerPC e CISC: X86 (or called IA32) Another divide: Superscalar, vllw and ePic o Superscalar: all the above O VLIW: Philips TriMEdia superscalar:[计算机]超标量体系结构 ●EPc:|A64 Under same ISA, there are many different processors a From different manufacturers. e X86 from Intel and AMd and via ■ Different models 0.80386 Pentium Pentium 4 Processor
– 8 – Processor Instruction Set Architecture #3 ISA define the processor family ◼ Two main kind: RISC and CISC ⚫ RISC:SPARC, MIPS, PowerPC ⚫ CISC:X86 (or called IA32) ◼ Another divide: Superscalar, VLIW and EPIC ⚫ Superscalar: all the above ⚫ VLIW: Philips TriMedia ⚫ EPIC: IA64 Under same ISA, there are many different processors ◼ From different manufacturers: ⚫ X86 from Intel and AMD and VIA ◼ Different models ⚫ 8086, 80386, Pentium, Pentium 4 superscalar:[计算机]超标量体系结构
Y86 Processor State P258 Floure 41 Program registers Condition Memory 号eax号esi codes ecx edi edx es PC 各ebx号eb Program Registers e Same 8 as with lA32. Each 32 bits ■ Condition codes e Single-bit flags set by arithmetic or logical instructions >)OF: Overflow ZF: Zero SF: Negative a Program Counter Indicates address of instruction ■ Memory o Byte-addressable storage array Words stored in little-endian byte order Processor
– 9 – Processor %eax %ecx %edx %ebx %esi %edi %esp %ebp Y86 Processor State ◼ Program Registers ⚫ Same 8 as with IA32. Each 32 bits ◼ Condition Codes ⚫ Single-bit flags set by arithmetic or logical instructions » OF: Overflow ZF: Zero SF:Negative ◼ Program Counter ⚫ Indicates address of instruction ◼ Memory ⚫ Byte-addressable storage array ⚫ Words stored in little-endian byte order Program registers Condition codes PC Memory OF ZF SF P258 Figure 4.1
Y86 Instructions P259 Flgure 4.2 Format(P259) a 1-6 bytes of information read from memory Can determine instruction length from first byte Not as many instruction types, and simpler encoding than with A32 Each accesses and modifies some part(s)of the program state Errata: JXX and call are 5 bytes long. -10 Processor
– 10 – Processor Y86 Instructions Format (P259) ◼ 1--6 bytes of information read from memory ⚫ Can determine instruction length from first byte ⚫ Not as many instruction types, and simpler encoding than with IA32 ◼ Each accesses and modifies some part(s) of the program state Errata: JXX and call are 5 bytes long. P259 Figure 4.2
