【例9-1】 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL ENTITY mux41 Is PORT(S4, S3, S2, SI: IN STD LOGIC; z4, z, Z2, zI: OUTSTD LOGIC); END mux41 arChitECtUrE activ of mux41 IS SIGNAL Sel INTEGER RANGEOTO 15 BEGIN PROCESS(Sel, s4, S3, S2, Sl) BEGIN sek<=0; 输入初始值 IF(sI=1) THEN sel < sel+l i 接下页接下页 【例9-1】 LIBRARY IEEE； USE IEEE.STD_LOGIC_1164.ALL； ENTITY mux41 IS PORT (s4，s3,s2，s1 : IN STD_LOGIC; z4，z3, z2，z1 : OUT STD_LOGIC); END mux41； ARCHITECTUREactiv OF mux41 IS SIGNAL sel : INTEGER RANGE 0 TO 15; BEGIN PROCESS (sel ，s4，s3，s2，s1 ) BEGIN sel<= 0 ; -- 输入初始值 IF (s1 ='1') THEN sel <= sel+1 ;