Is it correct ibrary ieee if(clk' event and clk='1)then when state0110=> if (serial in='1)then use ieee std logic 1164. all case present state when idle = if(serial in =0) next state < state01101 )then package your own type is match <=0 next state < stateo type t state is(idle, state0, state0l, state011 match <=0 state0110. state01101 match <='0 state011011) next state end your own type, when state01101=> if(serial in='1 )then library ieee when state serial in next state < state011011 match use ieee std logic 1164.all else use work. your own type. all next state < idle Entity sth is match <=0 port(clk, serial in: in std logic when state011011=> next state < idle match: out std logic) when (seral in ='l)then ate < state011 match <='0 end sth when others = next state < idle architecture body sth of sth match <=0. signal present state, next state next state < idle end case. begin match <=0 end if end process process(clk, serial in, present state) hen stateoll =>if( seral_ in=0)then present_state <=next_state, begin next state < state0110. next state < idle Copyright 1997 Altera Corporation match <=0 end if, 2/22/2021P10 favaraCopyright © 1997 Altera Corporation 2/22/2021 P.10 Is it correct ? when state0110 => if (serial_in = '1') then next_state <= state01101; match <= '0'; else next_state <= idle; match <= '0'; end if; when state01101 => if (serial_in = '1') then next_state <= state011011; match <= '1'; else next_state <= idle; match <= '0'; end if; when state011011 => next_state <= idle; match <= '0'; when others => next_state <= idle; match <= '0'; end case; end if; end process; present_state <= next_state; end body_stmh; library ieee; use ieee.std_logic_1164.all; package your_own_type is type t_state is (idle,state0,state01,state011, state0110,state01101, state011011); end your_own_type; library ieee; use ieee.std_logic_1164.all; use work.your_own_type.all; Entity stmh is port (clk, serial_in : in std_logic; match : out std_logic); end stmh; architecture body_stmh of stmh is signal present_state,next_state: t_state; begin process(clk,serial_in, present_state) begin if (clk'event and clk='1') then case present_state is when idle => if (serial_in = '0') then next_state <= state0; match <= '0'; else next_state <= idle; match <= '0'; end if; when state0 => if (serial_in = '1') then next_state <= state01; match <= '0'; else next_state <= idle; match <= '0'; end if; when state01 => if (serial_in = '1') then next_state <= state011; match <= '0'; else next_state <= idle; match <= '0'; end if; when state011 => if (serial_in = '0') then next_state <= state0110; match <= '0'; else next_state <= idle; match <= '0'; end if;