Section 1.12 Going Forward 23 boards for PCs),packaging constraints(e.g.,it has to fit in a toaster),or edicts from above(e.g.,in order to get the project approved three months ago,you fool- ishly told your manager that it would all fit on a 3x5 inch PCB,and now you've got to deliver!).In each of these cases,the cost of using a larger PCB or multiple PCBs may be unacceptable. Minimizing the number of ICs is usually the rule even though individual IC costs vary.For example,a typical SSIor MSI IC may cost 25 cents,while an small PLD may cost a dollar.It may be possible to perform a particular function with three SSI and MSI ICs(75 cents)or one PLD(a dollar).In most situations. the m ore expensive PLD solution is used,not because the designer owns stock in the IC company,but because the PLD solution uses less PCB area and is also a lot easier to change if it's not right the first time. In ASIC design,the name of the game is a little different,but the impor- ASIC design tance of structured,functional design techniques is the same.Although it's easy to burn hours and weeks creating custom macrocells and minimizing the total gate count of an ASIC,only rarely is this advisable.The per-unit cost reduction achieved by having a%smaller chip is negligible except in high-volume applications.In applications with low to medium volume(the majority),two other factors are more important:design time and NRE cost. A shorter design time allows a product to reach the market sooner,increas- ing revenues over the lifetime of the product.A lower NRE cost also flows right to the"bottom line,"and in small companies may be the only way the project can be completed before the company runs out of money (believe me,I've been there!).If the product is suc cessful,it's always possible and desi late to reduce perunit costs Thened o time and NRE cost argues in favor of a structured,as opposed to highly opti- mized,approach toASICdesign,using standard building blocks provided in the ASIC manufacturer's library. The considerations in PLD,CPLD,and FPGA design are a combination of the above.The choice of a particular PLD technology and device size is usually made fairly early in the design cycle.Later,as long as the design"fits"in the selected device,there's no point in trying to optimize gate count or board area- the device has already been committed.However,if new functions or bug fixes push the design beyond the capacity of the selected device that's when you mus work very hard to modify the design to make it fit. 1.12 Going Forward This concludes the introductory chapter.As you continue reading this book keep in mind two things.First,the ultimate goal of digital design is to build systems that solve problems for people.While this book will give you the basic tools for design,it's still your job to keep"the big picture"in the back of your mind.Second,cost is an important factor in every design decision;and you must Copyright 1999 by John F.Wakerly Copying ProhibitedSection 1.12 Going Forward 23 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited boards for PCs), packaging constraints (e.g., it has to fit in a toaster), or edicts from above (e.g., in order to get the project approved three months ago, you fool￾ishly told your manager that it would all fit on a 3 × 5 inch PCB, and now you’ve got to deliver!). In each of these cases, the cost of using a larger PCB or multiple PCBs may be unacceptable. Minimizing the number of ICs is usually the rule even though individual IC costs vary. For example, a typical SSI or MSI IC may cost 25 cents, while an small PLD may cost a dollar. It may be possible to perform a particular function with three SSI and MSI ICs (75 cents) or one PLD (a dollar). In most situations, the more expensive PLD solution is used, not because the designer owns stock in the IC company, but because the PLD solution uses less PCB area and is also a lot easier to change if it’s not right the first time. In ASIC design, the name of the game is a little different, but the impor￾tance of structured, functional design techniques is the same. Although it’s easy to burn hours and weeks creating custom macrocells and minimizing the total gate count of an ASIC, only rarely is this advisable. The per-unit cost reduction achieved by having a 10% smaller chip is negligible except in high-volume applications. In applications with low to medium volume (the majority), two other factors are more important: design time and NRE cost. A shorter design time allows a product to reach the market sooner, increas￾ing revenues over the lifetime of the product. A lower NRE cost also flows right to the “bottom line,” and in small companies may be the only way the project can be completed before the company runs out of money (believe me, I’ve been there!). If the product is successful, it’s always possible and profitable to “tweak” the design later to reduce per-unit costs. The need to minimize design time and NRE cost argues in favor of a structured, as opposed to highly opti￾mized, approach to ASIC design, using standard building blocks provided in the ASIC manufacturer’s library. The considerations in PLD, CPLD, and FPGA design are a combination of the above. The choice of a particular PLD technology and device size is usually made fairly early in the design cycle. Later, as long as the design “fits” in the selected device, there’s no point in trying to optimize gate count or board area— the device has already been committed. However, if new functions or bug fixes push the design beyond the capacity of the selected device, that’s when you must work very hard to modify the design to make it fit. 1.12 Going Forward This concludes the introductory chapter. As you continue reading this book, keep in mind two things. First, the ultimate goal of digital design is to build systems that solve problems for people. While this book will give you the basic tools for design, it’s still your job to keep “the big picture” in the back of your mind. Second, cost is an important factor in every design decision; and you must ASIC design