architecture one ofcnto is signal cnt std logic_vector(2 downto 0); signal clk_tmp: std logic, constant m: Integer:=5;-控制计数器的常量m=n/21 begin begin if clk event and clk=1 then if cnt=m the clk tmp<=1 cnt<="000; else clk_tmp<= 0 cnt<=cnt+1 end if end if: end process; div6<=clk_tmp; end onearchitecture one of cnt6 is signal cnt: std_logic_vector(2 downto 0); signal clk_tmp: std_logic; constant m:integer:=5; --控制计数器的常量m=n/2-1 begin process (clk) begin if clk’event and clk=‘1’ then if cnt=m then clk_tmp<= ‘1’; cnt<=“000”; else clk_tmp<=‘0’; cnt<=cnt+1; end if; end if; end process; div6<=clk_tmp; end one;